[v1,0/3] riscv: fix ptrace and export VLENB

Message

Andy Chiu Aug. 16, 2023, 3:54 p.m. UTC

We add a vlenb field in Vector context and save it with the
riscv_vstate_save() macro. It should not cause performance regression as
VLENB is a design-time constant and is frequently used by hardware.
Also, adding this field into the __sc_riscv_v_state may benifit us on a
future compatibility issue becuse a hardware may have writable VLENB.

Adding and saving VLENB have an immediate benifit as it gives ptrace a
better view of the Vector extension and makes it possible to reconstruct
Vector register files from the dump without doing an additional csr read.

This patchset also sync the number of note types between us and gdb for
riscv to solve a conflicting note.

This is not an ABI break given that 6.5 has not been released yet.

The series is tested on a virt QEMU by verifying VLENB is saved in
ptrace, coredump, and signal stack.

[1] https://sourceware.org/pipermail/gdb-patches/2023-August/201492.html

Andy Chiu (2):
  RISC-V: vector: export VLENB csr in __sc_riscv_v_state
  RISC-V: Add ptrace support for vectors

Palmer Dabbelt (1):
  RISC-V: Remove ptrace support for vectors

 arch/riscv/include/asm/vector.h      | 3 ++-
 arch/riscv/include/uapi/asm/ptrace.h | 1 +
 include/uapi/linux/elf.h             | 3 ++-
 3 files changed, 5 insertions(+), 2 deletions(-)

Comments

Maciej W. Rozycki Aug. 17, 2023, 12:35 p.m. UTC | #1

On Wed, 16 Aug 2023, Andy Chiu wrote:

> We add a vlenb field in Vector context and save it with the
> riscv_vstate_save() macro. It should not cause performance regression as
> VLENB is a design-time constant and is frequently used by hardware.
> Also, adding this field into the __sc_riscv_v_state may benifit us on a
> future compatibility issue becuse a hardware may have writable VLENB.
> 
> Adding and saving VLENB have an immediate benifit as it gives ptrace a
> better view of the Vector extension and makes it possible to reconstruct
> Vector register files from the dump without doing an additional csr read.

 I think it is an incorrect view of the situation.

 We need to include VLENB not to let a debugger avoid reading VLENB itself 
in its own context, but to have a complete view of the debuggee's register 
file.  While the ptrace(2) API has not been formally standardised by a 
body such as IEEE or The Open Group, our practice across ports has been to 
provide a complete view of the debuggee via ptrace(2) without a need to 
resort to examine the machine and OS on the debugger's side via other 
means.

 So we're not improving ptrace(2), but rather we're removing a defect.

  Maciej

[e-mail] Aug. 23, 2023, 7:40 p.m. UTC | #2

Hello:

This series was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <[e-mail]>:

On Wed, 16 Aug 2023 15:54:47 +0000 you wrote:
> We add a vlenb field in Vector context and save it with the
> riscv_vstate_save() macro. It should not cause performance regression as
> VLENB is a design-time constant and is frequently used by hardware.
> Also, adding this field into the __sc_riscv_v_state may benifit us on a
> future compatibility issue becuse a hardware may have writable VLENB.
> 
> Adding and saving VLENB have an immediate benifit as it gives ptrace a
> better view of the Vector extension and makes it possible to reconstruct
> Vector register files from the dump without doing an additional csr read.
> 
> [...]

Here is the summary with links:
  - [v1,1/3] RISC-V: Remove ptrace support for vectors
    https://git.kernel.org/riscv/c/e3f9324b231a
  - [v1,2/3] RISC-V: vector: export VLENB csr in __sc_riscv_v_state
    https://git.kernel.org/riscv/c/c35f3aa34509
  - [v1,3/3] RISC-V: Add ptrace support for vectors
    (no matching commit)

You are awesome, thank you!

Palmer Dabbelt Aug. 24, 2023, 8:08 p.m. UTC | #3

On Wed, 16 Aug 2023 15:54:47 +0000, Andy Chiu wrote:
> We add a vlenb field in Vector context and save it with the
> riscv_vstate_save() macro. It should not cause performance regression as
> VLENB is a design-time constant and is frequently used by hardware.
> Also, adding this field into the __sc_riscv_v_state may benifit us on a
> future compatibility issue becuse a hardware may have writable VLENB.
> 
> Adding and saving VLENB have an immediate benifit as it gives ptrace a
> better view of the Vector extension and makes it possible to reconstruct
> Vector register files from the dump without doing an additional csr read.
> 
> [...]

Applied, thanks!

[1/3] RISC-V: Remove ptrace support for vectors
      https://git.kernel.org/palmer/c/e3f9324b231a
[2/3] RISC-V: vector: export VLENB csr in __sc_riscv_v_state
      https://git.kernel.org/palmer/c/c35f3aa34509

Best regards,