diff mbox series

[v2,2/2] riscv: errata: prefix T-Head mnemonics with th.

Message ID 20230827090813.1353-3-jszhang@kernel.org (mailing list archive)
State Accepted
Commit c1c99e5f1b136130f48dd964fc1b2663530b41fa
Headers show
Series riscv: errata: improve T-Head CMO | expand

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conchuod/build_rv32_defconfig success Build OK
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Commit Message

Jisheng Zhang Aug. 27, 2023, 9:08 a.m. UTC 
From: Icenowy Zheng <uwu@icenowy.me>

T-Head now maintains some specification for their extended instructions
at [1], in which all instructions are prefixed "th.".

Follow this practice in the kernel comments.

Link: https://github.com/T-head-Semi/thead-extension-spec [1]
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
 arch/riscv/include/asm/errata_list.h | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

Comments

Guo Ren Aug. 27, 2023, 10:18 a.m. UTC | #1 
On Sun, Aug 27, 2023 at 5:20 AM Jisheng Zhang <jszhang@kernel.org> wrote:
>
> From: Icenowy Zheng <uwu@icenowy.me>
>
> T-Head now maintains some specification for their extended instructions
> at [1], in which all instructions are prefixed "th.".
>
> Follow this practice in the kernel comments.
>
> Link: https://github.com/T-head-Semi/thead-extension-spec [1]
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> ---
>  arch/riscv/include/asm/errata_list.h | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index feab334dd832..98ecab053dd2 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -90,25 +90,25 @@ asm volatile(ALTERNATIVE(                                           \
>  #endif
>
>  /*
> - * dcache.ipa rs1 (invalidate, physical address)
> + * th.dcache.ipa rs1 (invalidate, physical address)
>   * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
>   *   0000001    01010      rs1       000      00000  0001011
> - * dache.iva rs1 (invalida, virtual address)
> + * th.dache.iva rs1 (invalida, virtual address)
>   *   0000001    00110      rs1       000      00000  0001011
>   *
> - * dcache.cpa rs1 (clean, physical address)
> + * th.dcache.cpa rs1 (clean, physical address)
>   * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
>   *   0000001    01001      rs1       000      00000  0001011
> - * dcache.cva rs1 (clean, virtual address)
> + * th.dcache.cva rs1 (clean, virtual address)
>   *   0000001    00101      rs1       000      00000  0001011
>   *
> - * dcache.cipa rs1 (clean then invalidate, physical address)
> + * th.dcache.cipa rs1 (clean then invalidate, physical address)
>   * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
>   *   0000001    01011      rs1       000      00000  0001011
> - * dcache.civa rs1 (... virtual address)
> + * th.dcache.civa rs1 (... virtual address)
>   *   0000001    00111      rs1       000      00000  0001011
>   *
> - * sync.s (make sure all cache operations finished)
> + * th.sync.s (make sure all cache operations finished)
Reviewed-by: Guo Ren <guoren@kernel.org>

>   * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
>   *   0000000    11001     00000      000      00000  0001011
>   */
> --
> 2.40.1
>


--
Best Regards
 Guo Ren
diff mbox series

Patch

diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index feab334dd832..98ecab053dd2 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -90,25 +90,25 @@  asm volatile(ALTERNATIVE(						\
 #endif
 
 /*
- * dcache.ipa rs1 (invalidate, physical address)
+ * th.dcache.ipa rs1 (invalidate, physical address)
  * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
  *   0000001    01010      rs1       000      00000  0001011
- * dache.iva rs1 (invalida, virtual address)
+ * th.dache.iva rs1 (invalida, virtual address)
  *   0000001    00110      rs1       000      00000  0001011
  *
- * dcache.cpa rs1 (clean, physical address)
+ * th.dcache.cpa rs1 (clean, physical address)
  * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
  *   0000001    01001      rs1       000      00000  0001011
- * dcache.cva rs1 (clean, virtual address)
+ * th.dcache.cva rs1 (clean, virtual address)
  *   0000001    00101      rs1       000      00000  0001011
  *
- * dcache.cipa rs1 (clean then invalidate, physical address)
+ * th.dcache.cipa rs1 (clean then invalidate, physical address)
  * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
  *   0000001    01011      rs1       000      00000  0001011
- * dcache.civa rs1 (... virtual address)
+ * th.dcache.civa rs1 (... virtual address)
  *   0000001    00111      rs1       000      00000  0001011
  *
- * sync.s (make sure all cache operations finished)
+ * th.sync.s (make sure all cache operations finished)
  * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
  *   0000000    11001     00000      000      00000  0001011
  */