| Message ID | 20230724-th1520-emmc-v2-0-132ed2e2171e@baylibre.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | RISC-V: Add basic eMMC support for BeagleV Ahead | expand |
Hello, I tested the patch on my LicheePi 4A board. It can successfully boot with eMMC, but when I use the eMMC more frequently - for instance: $ while true; do /bin/dd if=/dev/zero of=bigfile bs=1024000 count=1024; done & I encounter the following error: sbi_trap_error: hart1: illegal instruction handler failed (error -2) sbi_trap_error: hart1: mcause=0x0000000000000002 mtval=0x0000000060e2de4f sbi_trap_error: hart1: mepc=0x000000000001897c mstatus=0x0000000a00001820 sbi_trap_error: hart1: ra=0x00000000000170f8 sp=0x000000000004adc8 sbi_trap_error: hart1: gp=0xffffffff8136ea90 tp=0xffffffd900228000 sbi_trap_error: hart1: s0=0x0000000000000000 s1=0x000000000004ae08 sbi_trap_error: hart1: a0=0x000000003f9aa9bc a1=0x0000000000000004 sbi_trap_error: hart1: a2=0x0000000000000000 a3=0x0000000000000000 sbi_trap_error: hart1: a4=0x0000000000042248 a5=0x00000000000170e5 sbi_trap_error: hart1: a6=0x0000000000000000 a7=0x0000000054494d45 sbi_trap_error: hart1: s2=0x000000000004aee8 s3=0x0000000000000000 sbi_trap_error: hart1: s4=0x000000000004ae08 s5=0x0000000000000000 sbi_trap_error: hart1: s6=0xffffffff813aa240 s7=0x0000000000000080 sbi_trap_error: hart1: s8=0xffffffff80a1b5f0 s9=0x0000000000000000 sbi_trap_error: hart1: s10=0xffffffd9fef5d380 s11=0xffffffff81290a80 sbi_trap_error: hart1: t0=0x0000000a00000820 t1=0x0000000000000000 sbi_trap_error: hart1: t2=0xffffffff80c00318 t3=0x0000000000000001 sbi_trap_error: hart1: t4=0x0000000000000330 t5=0x0000000000000001 sbi_trap_error: hart1: t6=0x0000000000040000 My kernel version is v6.5-rc3. My OpenSBI version is 1.3. I tried to use other versions of OpenSBI, yet the problem persists. Is there a possibility of any underlying bug? Your insights into this would be greatly appreciated. Thanks, Jiexun Wang
On Mon, Aug 28, 2023 at 12:40:16PM +0800, Jiexun Wang wrote: > Hello, > I tested the patch on my LicheePi 4A board. > It can successfully boot with eMMC, but when I use the eMMC more frequently - for instance: > > $ while true; do /bin/dd if=/dev/zero of=bigfile bs=1024000 count=1024; done & > > I encounter the following error: > > sbi_trap_error: hart1: illegal instruction handler failed (error -2) > sbi_trap_error: hart1: mcause=0x0000000000000002 mtval=0x0000000060e2de4f > sbi_trap_error: hart1: mepc=0x000000000001897c mstatus=0x0000000a00001820 > sbi_trap_error: hart1: ra=0x00000000000170f8 sp=0x000000000004adc8 > sbi_trap_error: hart1: gp=0xffffffff8136ea90 tp=0xffffffd900228000 > sbi_trap_error: hart1: s0=0x0000000000000000 s1=0x000000000004ae08 > sbi_trap_error: hart1: a0=0x000000003f9aa9bc a1=0x0000000000000004 > sbi_trap_error: hart1: a2=0x0000000000000000 a3=0x0000000000000000 > sbi_trap_error: hart1: a4=0x0000000000042248 a5=0x00000000000170e5 > sbi_trap_error: hart1: a6=0x0000000000000000 a7=0x0000000054494d45 > sbi_trap_error: hart1: s2=0x000000000004aee8 s3=0x0000000000000000 > sbi_trap_error: hart1: s4=0x000000000004ae08 s5=0x0000000000000000 > sbi_trap_error: hart1: s6=0xffffffff813aa240 s7=0x0000000000000080 > sbi_trap_error: hart1: s8=0xffffffff80a1b5f0 s9=0x0000000000000000 > sbi_trap_error: hart1: s10=0xffffffd9fef5d380 s11=0xffffffff81290a80 > sbi_trap_error: hart1: t0=0x0000000a00000820 t1=0x0000000000000000 > sbi_trap_error: hart1: t2=0xffffffff80c00318 t3=0x0000000000000001 > sbi_trap_error: hart1: t4=0x0000000000000330 t5=0x0000000000000001 > sbi_trap_error: hart1: t6=0x0000000000040000 > > My kernel version is v6.5-rc3. > My OpenSBI version is 1.3. > I tried to use other versions of OpenSBI, yet the problem persists. > Is there a possibility of any underlying bug? Your insights into this would be greatly appreciated. Can you plz try below opensbi? https://github.com/xhackerustc/thead-opensbi.git
Date: Mon, 28 Aug 2023 23:05:35 +0800, Jisheng Zhang wrote: >On Mon, Aug 28, 2023 at 12:40:16PM +0800, Jiexun Wang wrote: >> Hello, >> I tested the patch on my LicheePi 4A board. >> It can successfully boot with eMMC, but when I use the eMMC more frequently - for instance: >> >> $ while true; do /bin/dd if=/dev/zero of=bigfile bs=1024000 count=1024; done & >> >> I encounter the following error: >> >> sbi_trap_error: hart1: illegal instruction handler failed (error -2) > >> sbi_trap_error: hart1: mcause=0x0000000000000002 mtval=0x0000000060e2de4f >> sbi_trap_error: hart1: mepc=0x000000000001897c mstatus=0x0000000a00001820 >> sbi_trap_error: hart1: ra=0x00000000000170f8 sp=0x000000000004adc8 >> sbi_trap_error: hart1: gp=0xffffffff8136ea90 tp=0xffffffd900228000 >> sbi_trap_error: hart1: s0=0x0000000000000000 s1=0x000000000004ae08 >> sbi_trap_error: hart1: a0=0x000000003f9aa9bc a1=0x0000000000000004 >> sbi_trap_error: hart1: a2=0x0000000000000000 a3=0x0000000000000000 >> sbi_trap_error: hart1: a4=0x0000000000042248 a5=0x00000000000170e5 >> sbi_trap_error: hart1: a6=0x0000000000000000 a7=0x0000000054494d45 >> sbi_trap_error: hart1: s2=0x000000000004aee8 s3=0x0000000000000000 >> sbi_trap_error: hart1: s4=0x000000000004ae08 s5=0x0000000000000000 >> sbi_trap_error: hart1: s6=0xffffffff813aa240 s7=0x0000000000000080 >> sbi_trap_error: hart1: s8=0xffffffff80a1b5f0 s9=0x0000000000000000 >> sbi_trap_error: hart1: s10=0xffffffd9fef5d380 s11=0xffffffff81290a80 >> sbi_trap_error: hart1: t0=0x0000000a00000820 t1=0x0000000000000000 >> sbi_trap_error: hart1: t2=0xffffffff80c00318 t3=0x0000000000000001 >> sbi_trap_error: hart1: t4=0x0000000000000330 t5=0x0000000000000001 >> sbi_trap_error: hart1: t6=0x0000000000040000 >> >> My kernel version is v6.5-rc3. >> My OpenSBI version is 1.3. >> I tried to use other versions of OpenSBI, yet the problem persists. >> Is there a possibility of any underlying bug? Your insights into this would be greatly appreciated. > > >Can you plz try below opensbi? I tried the OpenSBI you provided and the issue didn't recur. I conducted stress test about 30 minutes and the system appears to be functioning very well. Thank you so much for helping me resolve this problem. Best regards, Jiexun Wang
On Tue, Aug 29, 2023 at 09:56:47AM +0800, Jiexun Wang wrote: > Date: Mon, 28 Aug 2023 23:05:35 +0800, Jisheng Zhang wrote: > >On Mon, Aug 28, 2023 at 12:40:16PM +0800, Jiexun Wang wrote: > >> Hello, > >> I tested the patch on my LicheePi 4A board. > >> It can successfully boot with eMMC, but when I use the eMMC more frequently - for instance: > >> > >> $ while true; do /bin/dd if=/dev/zero of=bigfile bs=1024000 count=1024; done & > >> > >> I encounter the following error: > >> > >> sbi_trap_error: hart1: illegal instruction handler failed (error -2) > > > >> sbi_trap_error: hart1: mcause=0x0000000000000002 mtval=0x0000000060e2de4f > >> sbi_trap_error: hart1: mepc=0x000000000001897c mstatus=0x0000000a00001820 > >> sbi_trap_error: hart1: ra=0x00000000000170f8 sp=0x000000000004adc8 > >> sbi_trap_error: hart1: gp=0xffffffff8136ea90 tp=0xffffffd900228000 > >> sbi_trap_error: hart1: s0=0x0000000000000000 s1=0x000000000004ae08 > >> sbi_trap_error: hart1: a0=0x000000003f9aa9bc a1=0x0000000000000004 > >> sbi_trap_error: hart1: a2=0x0000000000000000 a3=0x0000000000000000 > >> sbi_trap_error: hart1: a4=0x0000000000042248 a5=0x00000000000170e5 > >> sbi_trap_error: hart1: a6=0x0000000000000000 a7=0x0000000054494d45 > >> sbi_trap_error: hart1: s2=0x000000000004aee8 s3=0x0000000000000000 > >> sbi_trap_error: hart1: s4=0x000000000004ae08 s5=0x0000000000000000 > >> sbi_trap_error: hart1: s6=0xffffffff813aa240 s7=0x0000000000000080 > >> sbi_trap_error: hart1: s8=0xffffffff80a1b5f0 s9=0x0000000000000000 > >> sbi_trap_error: hart1: s10=0xffffffd9fef5d380 s11=0xffffffff81290a80 > >> sbi_trap_error: hart1: t0=0x0000000a00000820 t1=0x0000000000000000 > >> sbi_trap_error: hart1: t2=0xffffffff80c00318 t3=0x0000000000000001 > >> sbi_trap_error: hart1: t4=0x0000000000000330 t5=0x0000000000000001 > >> sbi_trap_error: hart1: t6=0x0000000000040000 > >> > >> My kernel version is v6.5-rc3. > >> My OpenSBI version is 1.3. > >> I tried to use other versions of OpenSBI, yet the problem persists. > >> Is there a possibility of any underlying bug? Your insights into this would be greatly appreciated. > > > > > >Can you plz try below opensbi? > > I tried the OpenSBI you provided and the issue didn't recur. > I conducted stress test about 30 minutes and the system appears to be functioning very well. > Thank you so much for helping me resolve this problem. That's great! Jisheng - are these the commits that fix the error? d98da90a19b5 ("lib: sbi_illegal_insn: Fix FENCE.TSO emulation infinite trap loop") 39d1e698c975 ("lib: sbi_illegal_insn: Add emulation for fence.tso") thanks, drew
On Tue, Aug 29, 2023 at 08:19:53AM -0700, Drew Fustini wrote: > On Tue, Aug 29, 2023 at 09:56:47AM +0800, Jiexun Wang wrote: > > Date: Mon, 28 Aug 2023 23:05:35 +0800, Jisheng Zhang wrote: > > >On Mon, Aug 28, 2023 at 12:40:16PM +0800, Jiexun Wang wrote: > > >> Hello, > > >> I tested the patch on my LicheePi 4A board. > > >> It can successfully boot with eMMC, but when I use the eMMC more frequently - for instance: > > >> > > >> $ while true; do /bin/dd if=/dev/zero of=bigfile bs=1024000 count=1024; done & > > >> > > >> I encounter the following error: > > >> > > >> sbi_trap_error: hart1: illegal instruction handler failed (error -2) > > > > > >> sbi_trap_error: hart1: mcause=0x0000000000000002 mtval=0x0000000060e2de4f > > >> sbi_trap_error: hart1: mepc=0x000000000001897c mstatus=0x0000000a00001820 > > >> sbi_trap_error: hart1: ra=0x00000000000170f8 sp=0x000000000004adc8 > > >> sbi_trap_error: hart1: gp=0xffffffff8136ea90 tp=0xffffffd900228000 > > >> sbi_trap_error: hart1: s0=0x0000000000000000 s1=0x000000000004ae08 > > >> sbi_trap_error: hart1: a0=0x000000003f9aa9bc a1=0x0000000000000004 > > >> sbi_trap_error: hart1: a2=0x0000000000000000 a3=0x0000000000000000 > > >> sbi_trap_error: hart1: a4=0x0000000000042248 a5=0x00000000000170e5 > > >> sbi_trap_error: hart1: a6=0x0000000000000000 a7=0x0000000054494d45 > > >> sbi_trap_error: hart1: s2=0x000000000004aee8 s3=0x0000000000000000 > > >> sbi_trap_error: hart1: s4=0x000000000004ae08 s5=0x0000000000000000 > > >> sbi_trap_error: hart1: s6=0xffffffff813aa240 s7=0x0000000000000080 > > >> sbi_trap_error: hart1: s8=0xffffffff80a1b5f0 s9=0x0000000000000000 > > >> sbi_trap_error: hart1: s10=0xffffffd9fef5d380 s11=0xffffffff81290a80 > > >> sbi_trap_error: hart1: t0=0x0000000a00000820 t1=0x0000000000000000 > > >> sbi_trap_error: hart1: t2=0xffffffff80c00318 t3=0x0000000000000001 > > >> sbi_trap_error: hart1: t4=0x0000000000000330 t5=0x0000000000000001 > > >> sbi_trap_error: hart1: t6=0x0000000000040000 > > >> > > >> My kernel version is v6.5-rc3. > > >> My OpenSBI version is 1.3. > > >> I tried to use other versions of OpenSBI, yet the problem persists. > > >> Is there a possibility of any underlying bug? Your insights into this would be greatly appreciated. > > > > > > > > >Can you plz try below opensbi? > > > > I tried the OpenSBI you provided and the issue didn't recur. > > I conducted stress test about 30 minutes and the system appears to be functioning very well. > > Thank you so much for helping me resolve this problem. > > That's great! > > Jisheng - are these the commits that fix the error? > > d98da90a19b5 ("lib: sbi_illegal_insn: Fix FENCE.TSO emulation infinite trap loop") > 39d1e698c975 ("lib: sbi_illegal_insn: Add emulation for fence.tso") > These two commits have been in upstream OpenSBI, so there must be something to be patched/fixed in the upstream OpenSBI, but I have not yet bisected the upstream OpenSBI to find the root cause. This issue is on my TODO list.
This series adds initial support for the eMMC on the BeagleV Ahead board. This allows the kernel to boot with the root fs on eMMC. I tested [1] on top of v6.5-rc3 with this config [2] along with the prerequisite series [3] that adds the BeagleV Ahead dts file. I am submitting this as an RFC for other people that want to test booting from the eMMC with mainline. There are several issues that need to be resolved before this code can progress beyond an RFC: - Only the MMC controller connected to the eMMC is enabled. I did not yet attempt to configure or use the microSD card slot. - The thead,th1520-dwcmshc compatible sets quirks which disable DMA and forces the use of inefficient PIO mode. I need to determine the correct configuration for the SDMA and ADMA modes. - th1520-specific code is needed in dwcmshc_set_uhs_signaling() for MMC_TIMING_MMC_HS400. I have not figured out add proper way to make that code conditional so that it only runs on th1520. One method could be to add a th1520 flag to dwcmshc_priv but that seems like a hack. Alternatively, set_uhs_signaling in sdhci_dwcmshc_th1520_ops could point to a th1520-specific function, but that new function would have to duplicate all the code in the current dwcmshc_set_uhs_signaling(). NOTE: I combined schema, dts and driver patches into this one series to simplify review and testing of this RFC. References: [1] https://gist.github.com/pdp7/09995be1e30df0a04b9b9cd31420f9d5 [2] https://gist.github.com/pdp7/e4585311eb2cd27df7b50c87babc15fd [3] https://lore.kernel.org/linux-riscv/20230722-upstream-beaglev-ahead-dts-v2-0-a470ab8fe806@baylibre.com/ Changes in v2: - Expand dwcmshc_priv based on driver in the T-Head 5.10 kernel: delay_line, non_removable, pull_up_en, io_fixed_1v8 - New boolean property "thead,pull-up" indicates phy pull-up config - New boolean property "thead,io-fixed-1v8" indicates that io voltage should be set to 1.8V during reset - Add th1520_phy_1_8v_init() as voltage_switch op - Add th1520_execute_tuning() as the platform_execute_tuning op - Added th1520_sdhci_reset() as the .reset op. This function will set io voltage to 1.8V after calling the standard sdhci_reset() function. - Modified dwcmshc_set_uhs_signaling() to enable SDHCI_CTRL_VDD_180 when io_fixed_1v8 is true - Add many defines for register offsets and settings based on the mmc support in the T-Head downstream v5.10 kernel v1 series: https://lore.kernel.org/r/20230724-th1520-emmc-v1-0-cca1b2533da2@baylibre.com Signed-off-by: Drew Fustini <dfustini@baylibre.com> --- Drew Fustini (4): dt-bindings: mmc: sdhci-of-dwcmhsc: Add T-Head TH1520 support riscv: dts: thead: Add TH1520 mmc controller and sdhci clock riscv: dts: thead: Enable BeagleV Ahead eMMC controller mmc: sdhci-of-dwcmshc: Add support for T-Head TH1520 .../bindings/mmc/snps,dwcmshc-sdhci.yaml | 9 + arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 17 ++ arch/riscv/boot/dts/thead/th1520.dtsi | 17 ++ drivers/mmc/host/sdhci-of-dwcmshc.c | 336 +++++++++++++++++++++ 4 files changed, 379 insertions(+) --- base-commit: cb8c874afdc063290797ae1776a5d410fecb06cb change-id: 20230724-th1520-emmc-73cde98805d6 Best regards,