| Message ID | 20230828054140.28054-4-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: VRR and M/N stuff | expand |
This looks good to me, Reviewed-by: Manasi Navare <navaremanasi@chromium.org> Manasi On Sun, Aug 27, 2023 at 10:41 PM Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Pull the vblank evasion scanline calculations into their own helper > to declutter intel_pipe_update_start() a bit. > > Cc: Manasi Navare <navaremanasi@chromium.org> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_crtc.c | 53 +++++++++++++---------- > 1 file changed, 31 insertions(+), 22 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c > index 461949b48411..e46a15d59d79 100644 > --- a/drivers/gpu/drm/i915/display/intel_crtc.c > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c > @@ -468,6 +468,36 @@ static int intel_mode_vblank_start(const struct drm_display_mode *mode) > return vblank_start; > } > > +static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state, > + struct intel_crtc *crtc, > + int *min, int *max, int *vblank_start) > +{ > + const struct intel_crtc_state *new_crtc_state = > + intel_atomic_get_new_crtc_state(state, crtc); > + const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode; > + > + if (new_crtc_state->vrr.enable) { > + if (intel_vrr_is_push_sent(new_crtc_state)) > + *vblank_start = intel_vrr_vmin_vblank_start(new_crtc_state); > + else > + *vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state); > + } else { > + *vblank_start = intel_mode_vblank_start(adjusted_mode); > + } > + > + /* FIXME needs to be calibrated sensibly */ > + *min = *vblank_start - intel_usecs_to_scanlines(adjusted_mode, > + VBLANK_EVASION_TIME_US); > + *max = *vblank_start - 1; > + > + /* > + * M/N is double buffered on the transcoder's undelayed vblank, > + * so with seamless M/N we must evade both vblanks. > + */ > + if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) > + *min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay; > +} > + > /** > * intel_pipe_update_start() - start update of a set of display registers > * @state: the atomic state > @@ -487,7 +517,6 @@ void intel_pipe_update_start(struct intel_atomic_state *state, > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > struct intel_crtc_state *new_crtc_state = > intel_atomic_get_new_crtc_state(state, crtc); > - const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode; > long timeout = msecs_to_jiffies_timeout(1); > int scanline, min, max, vblank_start; > wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); > @@ -503,27 +532,7 @@ void intel_pipe_update_start(struct intel_atomic_state *state, > if (intel_crtc_needs_vblank_work(new_crtc_state)) > intel_crtc_vblank_work_init(new_crtc_state); > > - if (new_crtc_state->vrr.enable) { > - if (intel_vrr_is_push_sent(new_crtc_state)) > - vblank_start = intel_vrr_vmin_vblank_start(new_crtc_state); > - else > - vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state); > - } else { > - vblank_start = intel_mode_vblank_start(adjusted_mode); > - } > - > - /* FIXME needs to be calibrated sensibly */ > - min = vblank_start - intel_usecs_to_scanlines(adjusted_mode, > - VBLANK_EVASION_TIME_US); > - max = vblank_start - 1; > - > - /* > - * M/N is double buffered on the transcoder's undelayed vblank, > - * so with seamless M/N we must evade both vblanks. > - */ > - if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) > - min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay; > - > + intel_crtc_vblank_evade_scanlines(state, crtc, &min, &max, &vblank_start); > if (min <= 0 || max <= 0) > goto irq_disable; > > -- > 2.41.0 >
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 461949b48411..e46a15d59d79 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -468,6 +468,36 @@ static int intel_mode_vblank_start(const struct drm_display_mode *mode) return vblank_start; } +static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state, + struct intel_crtc *crtc, + int *min, int *max, int *vblank_start) +{ + const struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode; + + if (new_crtc_state->vrr.enable) { + if (intel_vrr_is_push_sent(new_crtc_state)) + *vblank_start = intel_vrr_vmin_vblank_start(new_crtc_state); + else + *vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state); + } else { + *vblank_start = intel_mode_vblank_start(adjusted_mode); + } + + /* FIXME needs to be calibrated sensibly */ + *min = *vblank_start - intel_usecs_to_scanlines(adjusted_mode, + VBLANK_EVASION_TIME_US); + *max = *vblank_start - 1; + + /* + * M/N is double buffered on the transcoder's undelayed vblank, + * so with seamless M/N we must evade both vblanks. + */ + if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) + *min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay; +} + /** * intel_pipe_update_start() - start update of a set of display registers * @state: the atomic state @@ -487,7 +517,6 @@ void intel_pipe_update_start(struct intel_atomic_state *state, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode; long timeout = msecs_to_jiffies_timeout(1); int scanline, min, max, vblank_start; wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); @@ -503,27 +532,7 @@ void intel_pipe_update_start(struct intel_atomic_state *state, if (intel_crtc_needs_vblank_work(new_crtc_state)) intel_crtc_vblank_work_init(new_crtc_state); - if (new_crtc_state->vrr.enable) { - if (intel_vrr_is_push_sent(new_crtc_state)) - vblank_start = intel_vrr_vmin_vblank_start(new_crtc_state); - else - vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state); - } else { - vblank_start = intel_mode_vblank_start(adjusted_mode); - } - - /* FIXME needs to be calibrated sensibly */ - min = vblank_start - intel_usecs_to_scanlines(adjusted_mode, - VBLANK_EVASION_TIME_US); - max = vblank_start - 1; - - /* - * M/N is double buffered on the transcoder's undelayed vblank, - * so with seamless M/N we must evade both vblanks. - */ - if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) - min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay; - + intel_crtc_vblank_evade_scanlines(state, crtc, &min, &max, &vblank_start); if (min <= 0 || max <= 0) goto irq_disable;