| Message ID | 1693250307-8910-2-git-send-email-quic_srichara@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add support for IPQ5018 tsens | expand |
On 28/08/2023 21:18, Sricharan Ramabadhran wrote: > IPQ5018 has tsens v1.0 block with 4 sensors and 1 interrupt. > > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> > --- > .../bindings/thermal/qcom-tsens.yaml | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml > index 27e9e16e6455..2309bb6dce1b 100644 > --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml > +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml > @@ -42,6 +42,7 @@ properties: > - qcom,msm8956-tsens > - qcom,msm8976-tsens > - qcom,qcs404-tsens > + - qcom,ipq5018-tsens This does not look like placed in alphanumeric order. > - const: qcom,tsens-v1 > > - description: v2 of TSENS > @@ -409,4 +410,22 @@ examples: > #qcom,sensors = <16>; > #thermal-sensor-cells = <1>; > }; > + > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + // Example 5 (for any IPQ5018 based SoC-s): No need for new example for a difference in compatible. Drop it. Best regards, Krzysztof
Hi Krzysztof, On 8/29/2023 12:51 AM, Krzysztof Kozlowski wrote: > On 28/08/2023 21:18, Sricharan Ramabadhran wrote: >> IPQ5018 has tsens v1.0 block with 4 sensors and 1 interrupt. >> >> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> >> --- >> .../bindings/thermal/qcom-tsens.yaml | 19 +++++++++++++++++++ >> 1 file changed, 19 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml >> index 27e9e16e6455..2309bb6dce1b 100644 >> --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml >> +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml >> @@ -42,6 +42,7 @@ properties: >> - qcom,msm8956-tsens >> - qcom,msm8976-tsens >> - qcom,qcs404-tsens >> + - qcom,ipq5018-tsens > > This does not look like placed in alphanumeric order. > ok, will sort. >> - const: qcom,tsens-v1 >> >> - description: v2 of TSENS >> @@ -409,4 +410,22 @@ examples: >> #qcom,sensors = <16>; >> #thermal-sensor-cells = <1>; >> }; >> + >> + - | >> + #include <dt-bindings/interrupt-controller/arm-gic.h> >> + // Example 5 (for any IPQ5018 based SoC-s): > > No need for new example for a difference in compatible. Drop it. ok, will drop it. Regards, Sricharan
diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 27e9e16e6455..2309bb6dce1b 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -42,6 +42,7 @@ properties: - qcom,msm8956-tsens - qcom,msm8976-tsens - qcom,qcs404-tsens + - qcom,ipq5018-tsens - const: qcom,tsens-v1 - description: v2 of TSENS @@ -409,4 +410,22 @@ examples: #qcom,sensors = <16>; #thermal-sensor-cells = <1>; }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + // Example 5 (for any IPQ5018 based SoC-s): + tsens5: thermal-sensor@4a9000 { + compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1"; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SORT */ + + nvmem-cells = <&tsens_calib>; + nvmem-cell-names = "calib"; + + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; + + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; ...
IPQ5018 has tsens v1.0 block with 4 sensors and 1 interrupt. Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> --- .../bindings/thermal/qcom-tsens.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)