diff mbox series

Revert "drm/amd/display: Remove v_startup workaround for dcn3+"

Message ID 20230829201042.322173-1-hamza.mahfooz@amd.com (mailing list archive)
State New, archived
Headers show
Series Revert "drm/amd/display: Remove v_startup workaround for dcn3+" | expand

Commit Message

Hamza Mahfooz Aug. 29, 2023, 8:10 p.m. UTC 
This reverts commit 3a31e8b89b7240d9a17ace8a1ed050bdcb560f9e.

We still need to call dcn20_adjust_freesync_v_startup() for older DCN3+
ASICs otherwise it can cause DP to HDMI 2.1 PCONs to fail to light up.
So, reintroduce the reverted code and limit it to ASICs older than
DCN31.

Cc: stable@vger.kernel.org
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2809
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
---
 .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c  | 24 ++++---------------
 1 file changed, 4 insertions(+), 20 deletions(-)

Comments

Harry Wentland Aug. 31, 2023, 7:13 p.m. UTC | #1 
On 2023-08-29 16:10, Hamza Mahfooz wrote:
> This reverts commit 3a31e8b89b7240d9a17ace8a1ed050bdcb560f9e.
> 

This isn't a straight-up revert. Please split it into a revert (git revert),
followed by a patch to limit the revert to < DCN_VERSION_3_1.

Harry

> We still need to call dcn20_adjust_freesync_v_startup() for older DCN3+
> ASICs otherwise it can cause DP to HDMI 2.1 PCONs to fail to light up.
> So, reintroduce the reverted code and limit it to ASICs older than
> DCN31.
> 
> Cc: stable@vger.kernel.org
> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2809
> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
> ---
>  .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c  | 24 ++++---------------
>  1 file changed, 4 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
> index 0989a0152ae8..0841176e8d6c 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
> @@ -1099,6 +1099,10 @@ void dcn20_calculate_dlg_params(struct dc *dc,
>  		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
>  						pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
>  		context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
> +		if (dc->ctx->dce_version < DCN_VERSION_3_1 &&
> +		    context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
> +			dcn20_adjust_freesync_v_startup(&context->res_ctx.pipe_ctx[i].stream->timing,
> +							&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);
>  
>  		pipe_idx++;
>  	}
> @@ -1927,7 +1931,6 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co
>  	int vlevel = 0;
>  	int pipe_split_from[MAX_PIPES];
>  	int pipe_cnt = 0;
> -	int i = 0;
>  	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
>  	DC_LOGGER_INIT(dc->ctx->logger);
>  
> @@ -1951,15 +1954,6 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co
>  	dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
>  	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
>  
> -	for (i = 0; i < dc->res_pool->pipe_count; i++) {
> -		if (!context->res_ctx.pipe_ctx[i].stream)
> -			continue;
> -		if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
> -			dcn20_adjust_freesync_v_startup(
> -				&context->res_ctx.pipe_ctx[i].stream->timing,
> -				&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);
> -	}
> -
>  	BW_VAL_TRACE_END_WATERMARKS();
>  
>  	goto validate_out;
> @@ -2232,7 +2226,6 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc,
>  	int vlevel = 0;
>  	int pipe_split_from[MAX_PIPES];
>  	int pipe_cnt = 0;
> -	int i = 0;
>  	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
>  	DC_LOGGER_INIT(dc->ctx->logger);
>  
> @@ -2261,15 +2254,6 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc,
>  	dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
>  	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
>  
> -	for (i = 0; i < dc->res_pool->pipe_count; i++) {
> -		if (!context->res_ctx.pipe_ctx[i].stream)
> -			continue;
> -		if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
> -			dcn20_adjust_freesync_v_startup(
> -				&context->res_ctx.pipe_ctx[i].stream->timing,
> -				&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);
> -	}
> -
>  	BW_VAL_TRACE_END_WATERMARKS();
>  
>  	goto validate_out;
diff mbox series

Patch

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index 0989a0152ae8..0841176e8d6c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -1099,6 +1099,10 @@  void dcn20_calculate_dlg_params(struct dc *dc,
 		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
 						pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
 		context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
+		if (dc->ctx->dce_version < DCN_VERSION_3_1 &&
+		    context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
+			dcn20_adjust_freesync_v_startup(&context->res_ctx.pipe_ctx[i].stream->timing,
+							&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);
 
 		pipe_idx++;
 	}
@@ -1927,7 +1931,6 @@  static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co
 	int vlevel = 0;
 	int pipe_split_from[MAX_PIPES];
 	int pipe_cnt = 0;
-	int i = 0;
 	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
 	DC_LOGGER_INIT(dc->ctx->logger);
 
@@ -1951,15 +1954,6 @@  static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co
 	dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
 	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
 
-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-		if (!context->res_ctx.pipe_ctx[i].stream)
-			continue;
-		if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
-			dcn20_adjust_freesync_v_startup(
-				&context->res_ctx.pipe_ctx[i].stream->timing,
-				&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);
-	}
-
 	BW_VAL_TRACE_END_WATERMARKS();
 
 	goto validate_out;
@@ -2232,7 +2226,6 @@  bool dcn21_validate_bandwidth_fp(struct dc *dc,
 	int vlevel = 0;
 	int pipe_split_from[MAX_PIPES];
 	int pipe_cnt = 0;
-	int i = 0;
 	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
 	DC_LOGGER_INIT(dc->ctx->logger);
 
@@ -2261,15 +2254,6 @@  bool dcn21_validate_bandwidth_fp(struct dc *dc,
 	dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
 	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
 
-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-		if (!context->res_ctx.pipe_ctx[i].stream)
-			continue;
-		if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
-			dcn20_adjust_freesync_v_startup(
-				&context->res_ctx.pipe_ctx[i].stream->timing,
-				&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);
-	}
-
 	BW_VAL_TRACE_END_WATERMARKS();
 
 	goto validate_out;