| Message ID | 20230901095100.3771188-1-william.tseng@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/dsi: let HW maintain HS-TRAIL and CLK_POST | expand |
On Fri, 01 Sep 2023, William Tseng <william.tseng@intel.com> wrote: > This change is to adjust TEOT timing and TCLK-POST timing so DSI > signaling can meet CTS specification. > > For clock lane, the measured TEOT may be changed from 142.64 ns to > 107.36 ns, which is less than (105 ns+12*UI) and is conformed to > mipi D-PHY v1.2 CTS v1.0. > > As to TCLK-POST, it may be changed from 133.44 ns to 178.72 ns, which > is greater than (60 ns+52*UI) and is conformed to the CTS standard. > > The computed UI is around 1.47 ns. The question is, why does the VBT define all this stuff, and when should it be used and when ignored? Also, this won't build. BR, Jani. > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> > Cc: Suraj Kandpal <suraj.kandpal@intel.com> > Cc: Lee Shawn C <shawn.c.lee@intel.com> > Signed-off-by: William Tseng <william.tseng@intel.com> > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 31 ++++---------------------- > 1 file changed, 4 insertions(+), 27 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c > index ad6488e9c2b2..4a13f467ca46 100644 > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > @@ -1819,10 +1819,10 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) > struct intel_connector *connector = intel_dsi->attached_connector; > struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; > u32 tlpx_ns; > - u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; > - u32 ths_prepare_ns, tclk_trail_ns; > + u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt; > + u32 ths_prepare_ns; > u32 hs_zero_cnt; > - u32 tclk_pre_cnt, tclk_post_cnt; > + u32 tclk_pre_cnt; > > tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); > > @@ -1853,14 +1853,6 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) > clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; > } > > - /* trail cnt in escape clocks*/ > - trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); > - if (trail_cnt > ICL_TRAIL_CNT_MAX) { > - drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", > - trail_cnt); > - trail_cnt = ICL_TRAIL_CNT_MAX; > - } > - > /* tclk pre count in escape clocks */ > tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); > if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { > @@ -1869,15 +1861,6 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) > tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; > } > > - /* tclk post count in escape clocks */ > - tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); > - if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) { > - drm_dbg_kms(&dev_priv->drm, > - "tclk_post_cnt out of range (%d)\n", > - tclk_post_cnt); > - tclk_post_cnt = ICL_TCLK_POST_CNT_MAX; > - } > - > /* hs zero cnt in escape clocks */ > hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - > ths_prepare_ns, tlpx_ns); > @@ -1902,19 +1885,13 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) > CLK_ZERO_OVERRIDE | > CLK_ZERO(clk_zero_cnt) | > CLK_PRE_OVERRIDE | > - CLK_PRE(tclk_pre_cnt) | > - CLK_POST_OVERRIDE | > - CLK_POST(tclk_post_cnt) | > - CLK_TRAIL_OVERRIDE | > - CLK_TRAIL(trail_cnt)); > + CLK_PRE(tclk_pre_cnt)); > > /* data lanes dphy timings */ > intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | > HS_PREPARE(prepare_cnt) | > HS_ZERO_OVERRIDE | > HS_ZERO(hs_zero_cnt) | > - HS_TRAIL_OVERRIDE | > - HS_TRAIL(trail_cnt) | > HS_EXIT_OVERRIDE | > HS_EXIT(exit_zero_cnt));
On Fri, Sep 01, 2023 at 05:51:00PM +0800, William Tseng wrote: > This change is to adjust TEOT timing and TCLK-POST timing so DSI > signaling can meet CTS specification. > > For clock lane, the measured TEOT may be changed from 142.64 ns to > 107.36 ns, which is less than (105 ns+12*UI) and is conformed to > mipi D-PHY v1.2 CTS v1.0. > > As to TCLK-POST, it may be changed from 133.44 ns to 178.72 ns, which > is greater than (60 ns+52*UI) and is conformed to the CTS standard. > > The computed UI is around 1.47 ns. > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> > Cc: Suraj Kandpal <suraj.kandpal@intel.com> > Cc: Lee Shawn C <shawn.c.lee@intel.com> > Signed-off-by: William Tseng <william.tseng@intel.com> > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 31 ++++---------------------- > 1 file changed, 4 insertions(+), 27 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c > index ad6488e9c2b2..4a13f467ca46 100644 > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > @@ -1819,10 +1819,10 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) > struct intel_connector *connector = intel_dsi->attached_connector; > struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; > u32 tlpx_ns; > - u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; > - u32 ths_prepare_ns, tclk_trail_ns; > + u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt; > + u32 ths_prepare_ns; > u32 hs_zero_cnt; > - u32 tclk_pre_cnt, tclk_post_cnt; > + u32 tclk_pre_cnt; > > tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); > > @@ -1853,14 +1853,6 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) > clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; > } > > - /* trail cnt in escape clocks*/ > - trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); > - if (trail_cnt > ICL_TRAIL_CNT_MAX) { > - drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", > - trail_cnt); > - trail_cnt = ICL_TRAIL_CNT_MAX; > - } > - > /* tclk pre count in escape clocks */ > tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); > if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { > @@ -1869,15 +1861,6 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) > tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; > } > > - /* tclk post count in escape clocks */ > - tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); > - if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) { > - drm_dbg_kms(&dev_priv->drm, > - "tclk_post_cnt out of range (%d)\n", > - tclk_post_cnt); > - tclk_post_cnt = ICL_TCLK_POST_CNT_MAX; > - } > - > /* hs zero cnt in escape clocks */ > hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - > ths_prepare_ns, tlpx_ns); > @@ -1902,19 +1885,13 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) > CLK_ZERO_OVERRIDE | > CLK_ZERO(clk_zero_cnt) | > CLK_PRE_OVERRIDE | > - CLK_PRE(tclk_pre_cnt) | > - CLK_POST_OVERRIDE | > - CLK_POST(tclk_post_cnt) | > - CLK_TRAIL_OVERRIDE | > - CLK_TRAIL(trail_cnt)); > + CLK_PRE(tclk_pre_cnt)); Windows seems set these overrides: icl clk DPHY: PREPARE,ZERO icl clk DSI: PREPARE,ZERO icl data DPHY: PREPARE,ZERO,EXIT icl data DSI: PREPARE,ZERO,EXIT tgl clk DPHY: PREPARE,ZERO (?) tgl clk DSI: PREPARE,ZERO,POST (?) tgl data DPHY: PREPARE,ZERO,EXIT tgl data DSI: PREPARE,ZERO,EXIT adl clk DPHY: PREPARE,ZERO (?) (also PRE for 2.0-2.5 GHz data rate) adl clk DSI: PREPARE,ZERO,POST (?) (also PRE for 2.0-2.5 GHz data rate) adl data DPHY: PREPARE,ZERO,EXIT adl data DSI : PREPARE,ZERO,EXIT Didn't see any justification for the weird mismatch between DSI vs. DPHY POST override on tgl+. Anyways, looks like removing TRAIL is not particularly controversial since Windows also never overrides it. So probably you should split that up into a separate patch. > > /* data lanes dphy timings */ > intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | > HS_PREPARE(prepare_cnt) | > HS_ZERO_OVERRIDE | > HS_ZERO(hs_zero_cnt) | > - HS_TRAIL_OVERRIDE | > - HS_TRAIL(trail_cnt) | > HS_EXIT_OVERRIDE | > HS_EXIT(exit_zero_cnt)); > > -- > 2.34.1
Hi William,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-tip/drm-tip]
url: https://github.com/intel-lab-lkp/linux/commits/William-Tseng/drm-i915-dsi-let-HW-maintain-HS-TRAIL-and-CLK_POST/20230901-175307
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link: https://lore.kernel.org/r/20230901095100.3771188-1-william.tseng%40intel.com
patch subject: [Intel-gfx] [PATCH] drm/i915/dsi: let HW maintain HS-TRAIL and CLK_POST
config: i386-randconfig-002-20230901 (https://download.01.org/0day-ci/archive/20230901/202309012009.7IXuIGBJ-lkp@intel.com/config)
compiler: clang version 16.0.4 (https://github.com/llvm/llvm-project.git ae42196bc493ffe877a7e3dff8be32035dea4d07)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230901/202309012009.7IXuIGBJ-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202309012009.7IXuIGBJ-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/icl_dsi.c:1829:2: error: use of undeclared identifier 'tclk_trail_ns'
tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
^
1 error generated.
vim +/tclk_trail_ns +1829 drivers/gpu/drm/i915/display/icl_dsi.c
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1814
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1815 static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1816 {
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1817 struct drm_device *dev = intel_dsi->base.base.dev;
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1818 struct drm_i915_private *dev_priv = to_i915(dev);
3cf050762534cc drivers/gpu/drm/i915/display/icl_dsi.c Ville Syrjälä 2022-05-10 1819 struct intel_connector *connector = intel_dsi->attached_connector;
3cf050762534cc drivers/gpu/drm/i915/display/icl_dsi.c Ville Syrjälä 2022-05-10 1820 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1821 u32 tlpx_ns;
78ef7b0ec18ccb drivers/gpu/drm/i915/display/icl_dsi.c William Tseng 2023-09-01 1822 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt;
78ef7b0ec18ccb drivers/gpu/drm/i915/display/icl_dsi.c William Tseng 2023-09-01 1823 u32 ths_prepare_ns;
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1824 u32 hs_zero_cnt;
78ef7b0ec18ccb drivers/gpu/drm/i915/display/icl_dsi.c William Tseng 2023-09-01 1825 u32 tclk_pre_cnt;
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1826
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1827 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1828
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 @1829 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1830 ths_prepare_ns = max(mipi_config->ths_prepare,
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1831 mipi_config->tclk_prepare);
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1832
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1833 /*
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1834 * prepare cnt in escape clocks
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1835 * this field represents a hexadecimal value with a precision
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1836 * of 1.2 – i.e. the most significant bit is the integer
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1837 * and the least significant 2 bits are fraction bits.
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1838 * so, the field can represent a range of 0.25 to 1.75
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1839 */
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1840 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1841 if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
b5280cd0bd2d68 drivers/gpu/drm/i915/display/icl_dsi.c Wambui Karuga 2020-01-22 1842 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n",
b5280cd0bd2d68 drivers/gpu/drm/i915/display/icl_dsi.c Wambui Karuga 2020-01-22 1843 prepare_cnt);
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1844 prepare_cnt = ICL_PREPARE_CNT_MAX;
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1845 }
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1846
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1847 /* clk zero count in escape clocks */
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1848 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1849 ths_prepare_ns, tlpx_ns);
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1850 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
b5280cd0bd2d68 drivers/gpu/drm/i915/display/icl_dsi.c Wambui Karuga 2020-01-22 1851 drm_dbg_kms(&dev_priv->drm,
b5280cd0bd2d68 drivers/gpu/drm/i915/display/icl_dsi.c Wambui Karuga 2020-01-22 1852 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1853 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1854 }
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1855
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1856 /* tclk pre count in escape clocks */
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1857 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1858 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
b5280cd0bd2d68 drivers/gpu/drm/i915/display/icl_dsi.c Wambui Karuga 2020-01-22 1859 drm_dbg_kms(&dev_priv->drm,
b5280cd0bd2d68 drivers/gpu/drm/i915/display/icl_dsi.c Wambui Karuga 2020-01-22 1860 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1861 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1862 }
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1863
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1864 /* hs zero cnt in escape clocks */
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1865 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1866 ths_prepare_ns, tlpx_ns);
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1867 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
b5280cd0bd2d68 drivers/gpu/drm/i915/display/icl_dsi.c Wambui Karuga 2020-01-22 1868 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n",
b5280cd0bd2d68 drivers/gpu/drm/i915/display/icl_dsi.c Wambui Karuga 2020-01-22 1869 hs_zero_cnt);
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1870 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1871 }
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1872
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1873 /* hs exit zero cnt in escape clocks */
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1874 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1875 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
b5280cd0bd2d68 drivers/gpu/drm/i915/display/icl_dsi.c Wambui Karuga 2020-01-22 1876 drm_dbg_kms(&dev_priv->drm,
b5280cd0bd2d68 drivers/gpu/drm/i915/display/icl_dsi.c Wambui Karuga 2020-01-22 1877 "exit_zero_cnt out of range (%d)\n",
b5280cd0bd2d68 drivers/gpu/drm/i915/display/icl_dsi.c Wambui Karuga 2020-01-22 1878 exit_zero_cnt);
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1879 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1880 }
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1881
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1882 /* clock lane dphy timings */
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1883 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1884 CLK_PREPARE(prepare_cnt) |
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1885 CLK_ZERO_OVERRIDE |
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1886 CLK_ZERO(clk_zero_cnt) |
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1887 CLK_PRE_OVERRIDE |
78ef7b0ec18ccb drivers/gpu/drm/i915/display/icl_dsi.c William Tseng 2023-09-01 1888 CLK_PRE(tclk_pre_cnt));
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1889
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1890 /* data lanes dphy timings */
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1891 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1892 HS_PREPARE(prepare_cnt) |
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1893 HS_ZERO_OVERRIDE |
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1894 HS_ZERO(hs_zero_cnt) |
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1895 HS_EXIT_OVERRIDE |
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1896 HS_EXIT(exit_zero_cnt));
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1897
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1898 intel_dsi_log_params(intel_dsi);
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1899 }
2def5ae7d7fb85 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1900
Hi William,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-tip/drm-tip]
url: https://github.com/intel-lab-lkp/linux/commits/William-Tseng/drm-i915-dsi-let-HW-maintain-HS-TRAIL-and-CLK_POST/20230901-175307
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link: https://lore.kernel.org/r/20230901095100.3771188-1-william.tseng%40intel.com
patch subject: [Intel-gfx] [PATCH] drm/i915/dsi: let HW maintain HS-TRAIL and CLK_POST
config: x86_64-defconfig (https://download.01.org/0day-ci/archive/20230901/202309012129.siE9g3DY-lkp@intel.com/config)
compiler: gcc-11 (Debian 11.3.0-12) 11.3.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230901/202309012129.siE9g3DY-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202309012129.siE9g3DY-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/display/icl_dsi.c: In function 'icl_dphy_param_init':
>> drivers/gpu/drm/i915/display/icl_dsi.c:1829:9: error: 'tclk_trail_ns' undeclared (first use in this function)
1829 | tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/display/icl_dsi.c:1829:9: note: each undeclared identifier is reported only once for each function it appears in
vim +/tclk_trail_ns +1829 drivers/gpu/drm/i915/display/icl_dsi.c
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1814
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1815 static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1816 {
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1817 struct drm_device *dev = intel_dsi->base.base.dev;
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1818 struct drm_i915_private *dev_priv = to_i915(dev);
3cf050762534cc2 drivers/gpu/drm/i915/display/icl_dsi.c Ville Syrjälä 2022-05-10 1819 struct intel_connector *connector = intel_dsi->attached_connector;
3cf050762534cc2 drivers/gpu/drm/i915/display/icl_dsi.c Ville Syrjälä 2022-05-10 1820 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1821 u32 tlpx_ns;
78ef7b0ec18ccb2 drivers/gpu/drm/i915/display/icl_dsi.c William Tseng 2023-09-01 1822 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt;
78ef7b0ec18ccb2 drivers/gpu/drm/i915/display/icl_dsi.c William Tseng 2023-09-01 1823 u32 ths_prepare_ns;
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1824 u32 hs_zero_cnt;
78ef7b0ec18ccb2 drivers/gpu/drm/i915/display/icl_dsi.c William Tseng 2023-09-01 1825 u32 tclk_pre_cnt;
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1826
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1827 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1828
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 @1829 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1830 ths_prepare_ns = max(mipi_config->ths_prepare,
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1831 mipi_config->tclk_prepare);
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1832
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1833 /*
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1834 * prepare cnt in escape clocks
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1835 * this field represents a hexadecimal value with a precision
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1836 * of 1.2 – i.e. the most significant bit is the integer
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1837 * and the least significant 2 bits are fraction bits.
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1838 * so, the field can represent a range of 0.25 to 1.75
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1839 */
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1840 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1841 if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
b5280cd0bd2d680 drivers/gpu/drm/i915/display/icl_dsi.c Wambui Karuga 2020-01-22 1842 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n",
b5280cd0bd2d680 drivers/gpu/drm/i915/display/icl_dsi.c Wambui Karuga 2020-01-22 1843 prepare_cnt);
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1844 prepare_cnt = ICL_PREPARE_CNT_MAX;
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1845 }
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1846
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1847 /* clk zero count in escape clocks */
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1848 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1849 ths_prepare_ns, tlpx_ns);
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1850 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
b5280cd0bd2d680 drivers/gpu/drm/i915/display/icl_dsi.c Wambui Karuga 2020-01-22 1851 drm_dbg_kms(&dev_priv->drm,
b5280cd0bd2d680 drivers/gpu/drm/i915/display/icl_dsi.c Wambui Karuga 2020-01-22 1852 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1853 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1854 }
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1855
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1856 /* tclk pre count in escape clocks */
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1857 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1858 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
b5280cd0bd2d680 drivers/gpu/drm/i915/display/icl_dsi.c Wambui Karuga 2020-01-22 1859 drm_dbg_kms(&dev_priv->drm,
b5280cd0bd2d680 drivers/gpu/drm/i915/display/icl_dsi.c Wambui Karuga 2020-01-22 1860 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1861 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1862 }
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1863
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1864 /* hs zero cnt in escape clocks */
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1865 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1866 ths_prepare_ns, tlpx_ns);
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1867 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
b5280cd0bd2d680 drivers/gpu/drm/i915/display/icl_dsi.c Wambui Karuga 2020-01-22 1868 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n",
b5280cd0bd2d680 drivers/gpu/drm/i915/display/icl_dsi.c Wambui Karuga 2020-01-22 1869 hs_zero_cnt);
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1870 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1871 }
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1872
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1873 /* hs exit zero cnt in escape clocks */
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1874 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1875 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
b5280cd0bd2d680 drivers/gpu/drm/i915/display/icl_dsi.c Wambui Karuga 2020-01-22 1876 drm_dbg_kms(&dev_priv->drm,
b5280cd0bd2d680 drivers/gpu/drm/i915/display/icl_dsi.c Wambui Karuga 2020-01-22 1877 "exit_zero_cnt out of range (%d)\n",
b5280cd0bd2d680 drivers/gpu/drm/i915/display/icl_dsi.c Wambui Karuga 2020-01-22 1878 exit_zero_cnt);
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1879 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1880 }
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1881
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1882 /* clock lane dphy timings */
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1883 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1884 CLK_PREPARE(prepare_cnt) |
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1885 CLK_ZERO_OVERRIDE |
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1886 CLK_ZERO(clk_zero_cnt) |
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1887 CLK_PRE_OVERRIDE |
78ef7b0ec18ccb2 drivers/gpu/drm/i915/display/icl_dsi.c William Tseng 2023-09-01 1888 CLK_PRE(tclk_pre_cnt));
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1889
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1890 /* data lanes dphy timings */
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1891 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1892 HS_PREPARE(prepare_cnt) |
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1893 HS_ZERO_OVERRIDE |
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1894 HS_ZERO(hs_zero_cnt) |
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1895 HS_EXIT_OVERRIDE |
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1896 HS_EXIT(exit_zero_cnt));
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1897
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1898 intel_dsi_log_params(intel_dsi);
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1899 }
2def5ae7d7fb857 drivers/gpu/drm/i915/icl_dsi.c Hans de Goede 2019-06-05 1900
For current VBT design, it does define the parameters ths_exit and tclk_post, which are related to the timing values, TEOT and TCLK-POST respectively. Unfortunately they are not configurable from VBT because both parameters are constants passed by VBT. To fix the timing problems, shall the VBT design be changed to make the two parameters adjustable? -----Original Message----- From: Jani Nikula <jani.nikula@linux.intel.com> Sent: Friday, September 1, 2023 6:28 PM To: Tseng, William <william.tseng@intel.com>; intel-gfx@lists.freedesktop.org Cc: Tseng, William <william.tseng@intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>; Kulkarni, Vandita <vandita.kulkarni@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>; Lee, Shawn C <shawn.c.lee@intel.com> Subject: Re: [PATCH] drm/i915/dsi: let HW maintain HS-TRAIL and CLK_POST On Fri, 01 Sep 2023, William Tseng <william.tseng@intel.com> wrote: > This change is to adjust TEOT timing and TCLK-POST timing so DSI > signaling can meet CTS specification. > > For clock lane, the measured TEOT may be changed from 142.64 ns to > 107.36 ns, which is less than (105 ns+12*UI) and is conformed to mipi > D-PHY v1.2 CTS v1.0. > > As to TCLK-POST, it may be changed from 133.44 ns to 178.72 ns, which > is greater than (60 ns+52*UI) and is conformed to the CTS standard. > > The computed UI is around 1.47 ns. The question is, why does the VBT define all this stuff, and when should it be used and when ignored? Also, this won't build. BR, Jani. > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> > Cc: Suraj Kandpal <suraj.kandpal@intel.com> > Cc: Lee Shawn C <shawn.c.lee@intel.com> > Signed-off-by: William Tseng <william.tseng@intel.com> > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 31 > ++++---------------------- > 1 file changed, 4 insertions(+), 27 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c > b/drivers/gpu/drm/i915/display/icl_dsi.c > index ad6488e9c2b2..4a13f467ca46 100644 > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > @@ -1819,10 +1819,10 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) > struct intel_connector *connector = intel_dsi->attached_connector; > struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; > u32 tlpx_ns; > - u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; > - u32 ths_prepare_ns, tclk_trail_ns; > + u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt; > + u32 ths_prepare_ns; > u32 hs_zero_cnt; > - u32 tclk_pre_cnt, tclk_post_cnt; > + u32 tclk_pre_cnt; > > tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); > > @@ -1853,14 +1853,6 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) > clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; > } > > - /* trail cnt in escape clocks*/ > - trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); > - if (trail_cnt > ICL_TRAIL_CNT_MAX) { > - drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", > - trail_cnt); > - trail_cnt = ICL_TRAIL_CNT_MAX; > - } > - > /* tclk pre count in escape clocks */ > tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); > if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { @@ -1869,15 +1861,6 @@ > static void icl_dphy_param_init(struct intel_dsi *intel_dsi) > tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; > } > > - /* tclk post count in escape clocks */ > - tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); > - if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) { > - drm_dbg_kms(&dev_priv->drm, > - "tclk_post_cnt out of range (%d)\n", > - tclk_post_cnt); > - tclk_post_cnt = ICL_TCLK_POST_CNT_MAX; > - } > - > /* hs zero cnt in escape clocks */ > hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - > ths_prepare_ns, tlpx_ns); > @@ -1902,19 +1885,13 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) > CLK_ZERO_OVERRIDE | > CLK_ZERO(clk_zero_cnt) | > CLK_PRE_OVERRIDE | > - CLK_PRE(tclk_pre_cnt) | > - CLK_POST_OVERRIDE | > - CLK_POST(tclk_post_cnt) | > - CLK_TRAIL_OVERRIDE | > - CLK_TRAIL(trail_cnt)); > + CLK_PRE(tclk_pre_cnt)); > > /* data lanes dphy timings */ > intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | > HS_PREPARE(prepare_cnt) | > HS_ZERO_OVERRIDE | > HS_ZERO(hs_zero_cnt) | > - HS_TRAIL_OVERRIDE | > - HS_TRAIL(trail_cnt) | > HS_EXIT_OVERRIDE | > HS_EXIT(exit_zero_cnt)); -- Jani Nikula, Intel Open Source Graphics Center
Thanks for the comment. I will revise this patch, so the change is only removing POST overriding. In addition, the patch for removing TRAIL was submitted as https://patchwork.kernel.org/project/intel-gfx/patch/20211217100903.32599-1-william.tseng@intel.com/. Can you help to review as well? -----Original Message----- From: Ville Syrjälä <ville.syrjala@linux.intel.com> Sent: Friday, September 1, 2023 6:53 PM To: Tseng, William <william.tseng@intel.com> Cc: intel-gfx@lists.freedesktop.org; Jani Nikula <jani.nikula@linux.intel.com>; Kulkarni, Vandita <vandita.kulkarni@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>; Lee, Shawn C <shawn.c.lee@intel.com> Subject: Re: [PATCH] drm/i915/dsi: let HW maintain HS-TRAIL and CLK_POST On Fri, Sep 01, 2023 at 05:51:00PM +0800, William Tseng wrote: > This change is to adjust TEOT timing and TCLK-POST timing so DSI > signaling can meet CTS specification. > > For clock lane, the measured TEOT may be changed from 142.64 ns to > 107.36 ns, which is less than (105 ns+12*UI) and is conformed to mipi > D-PHY v1.2 CTS v1.0. > > As to TCLK-POST, it may be changed from 133.44 ns to 178.72 ns, which > is greater than (60 ns+52*UI) and is conformed to the CTS standard. > > The computed UI is around 1.47 ns. > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> > Cc: Suraj Kandpal <suraj.kandpal@intel.com> > Cc: Lee Shawn C <shawn.c.lee@intel.com> > Signed-off-by: William Tseng <william.tseng@intel.com> > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 31 > ++++---------------------- > 1 file changed, 4 insertions(+), 27 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c > b/drivers/gpu/drm/i915/display/icl_dsi.c > index ad6488e9c2b2..4a13f467ca46 100644 > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > @@ -1819,10 +1819,10 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) > struct intel_connector *connector = intel_dsi->attached_connector; > struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; > u32 tlpx_ns; > - u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; > - u32 ths_prepare_ns, tclk_trail_ns; > + u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt; > + u32 ths_prepare_ns; > u32 hs_zero_cnt; > - u32 tclk_pre_cnt, tclk_post_cnt; > + u32 tclk_pre_cnt; > > tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); > > @@ -1853,14 +1853,6 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) > clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; > } > > - /* trail cnt in escape clocks*/ > - trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); > - if (trail_cnt > ICL_TRAIL_CNT_MAX) { > - drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", > - trail_cnt); > - trail_cnt = ICL_TRAIL_CNT_MAX; > - } > - > /* tclk pre count in escape clocks */ > tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); > if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { @@ -1869,15 +1861,6 @@ > static void icl_dphy_param_init(struct intel_dsi *intel_dsi) > tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; > } > > - /* tclk post count in escape clocks */ > - tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); > - if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) { > - drm_dbg_kms(&dev_priv->drm, > - "tclk_post_cnt out of range (%d)\n", > - tclk_post_cnt); > - tclk_post_cnt = ICL_TCLK_POST_CNT_MAX; > - } > - > /* hs zero cnt in escape clocks */ > hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - > ths_prepare_ns, tlpx_ns); > @@ -1902,19 +1885,13 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) > CLK_ZERO_OVERRIDE | > CLK_ZERO(clk_zero_cnt) | > CLK_PRE_OVERRIDE | > - CLK_PRE(tclk_pre_cnt) | > - CLK_POST_OVERRIDE | > - CLK_POST(tclk_post_cnt) | > - CLK_TRAIL_OVERRIDE | > - CLK_TRAIL(trail_cnt)); > + CLK_PRE(tclk_pre_cnt)); Windows seems set these overrides: icl clk DPHY: PREPARE,ZERO icl clk DSI: PREPARE,ZERO icl data DPHY: PREPARE,ZERO,EXIT icl data DSI: PREPARE,ZERO,EXIT tgl clk DPHY: PREPARE,ZERO (?) tgl clk DSI: PREPARE,ZERO,POST (?) tgl data DPHY: PREPARE,ZERO,EXIT tgl data DSI: PREPARE,ZERO,EXIT adl clk DPHY: PREPARE,ZERO (?) (also PRE for 2.0-2.5 GHz data rate) adl clk DSI: PREPARE,ZERO,POST (?) (also PRE for 2.0-2.5 GHz data rate) adl data DPHY: PREPARE,ZERO,EXIT adl data DSI : PREPARE,ZERO,EXIT Didn't see any justification for the weird mismatch between DSI vs. DPHY POST override on tgl+. Anyways, looks like removing TRAIL is not particularly controversial since Windows also never overrides it. So probably you should split that up into a separate patch. > > /* data lanes dphy timings */ > intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | > HS_PREPARE(prepare_cnt) | > HS_ZERO_OVERRIDE | > HS_ZERO(hs_zero_cnt) | > - HS_TRAIL_OVERRIDE | > - HS_TRAIL(trail_cnt) | > HS_EXIT_OVERRIDE | > HS_EXIT(exit_zero_cnt)); > > -- > 2.34.1 -- Ville Syrjälä Intel
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index ad6488e9c2b2..4a13f467ca46 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1819,10 +1819,10 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) struct intel_connector *connector = intel_dsi->attached_connector; struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; u32 tlpx_ns; - u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; - u32 ths_prepare_ns, tclk_trail_ns; + u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt; + u32 ths_prepare_ns; u32 hs_zero_cnt; - u32 tclk_pre_cnt, tclk_post_cnt; + u32 tclk_pre_cnt; tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); @@ -1853,14 +1853,6 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; } - /* trail cnt in escape clocks*/ - trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); - if (trail_cnt > ICL_TRAIL_CNT_MAX) { - drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", - trail_cnt); - trail_cnt = ICL_TRAIL_CNT_MAX; - } - /* tclk pre count in escape clocks */ tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { @@ -1869,15 +1861,6 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; } - /* tclk post count in escape clocks */ - tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); - if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) { - drm_dbg_kms(&dev_priv->drm, - "tclk_post_cnt out of range (%d)\n", - tclk_post_cnt); - tclk_post_cnt = ICL_TCLK_POST_CNT_MAX; - } - /* hs zero cnt in escape clocks */ hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - ths_prepare_ns, tlpx_ns); @@ -1902,19 +1885,13 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) CLK_ZERO_OVERRIDE | CLK_ZERO(clk_zero_cnt) | CLK_PRE_OVERRIDE | - CLK_PRE(tclk_pre_cnt) | - CLK_POST_OVERRIDE | - CLK_POST(tclk_post_cnt) | - CLK_TRAIL_OVERRIDE | - CLK_TRAIL(trail_cnt)); + CLK_PRE(tclk_pre_cnt)); /* data lanes dphy timings */ intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | HS_PREPARE(prepare_cnt) | HS_ZERO_OVERRIDE | HS_ZERO(hs_zero_cnt) | - HS_TRAIL_OVERRIDE | - HS_TRAIL(trail_cnt) | HS_EXIT_OVERRIDE | HS_EXIT(exit_zero_cnt));
This change is to adjust TEOT timing and TCLK-POST timing so DSI signaling can meet CTS specification. For clock lane, the measured TEOT may be changed from 142.64 ns to 107.36 ns, which is less than (105 ns+12*UI) and is conformed to mipi D-PHY v1.2 CTS v1.0. As to TCLK-POST, it may be changed from 133.44 ns to 178.72 ns, which is greater than (60 ns+52*UI) and is conformed to the CTS standard. The computed UI is around 1.47 ns. Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Lee Shawn C <shawn.c.lee@intel.com> Signed-off-by: William Tseng <william.tseng@intel.com> --- drivers/gpu/drm/i915/display/icl_dsi.c | 31 ++++---------------------- 1 file changed, 4 insertions(+), 27 deletions(-)