Message ID | 1693889975-19122-1-git-send-email-quic_rohiagar@quicinc.com (mailing list archive) |
---|---|
Headers | show |
Series | Add interconnect driver for SDX75 | expand |
On 9/5/2023 12:32 PM, Krzysztof Kozlowski wrote: > On 05/09/2023 06:59, Rohit Agarwal wrote: >> Add driver for the Qualcomm interconnect buses found in SDX75. >> >> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> > ... > >> + >> +static struct qcom_icc_bcm *system_noc_bcms[] = { > Please do not copy your code from downstream, but work on upstream. We > changed this long time ago, so you clearly used some old or obsolete > file as template. Sure will check the sm8550 as template and work on it again. Thank you for your time. Thanks, Rohit. >> + &bcm_ce0, >> + &bcm_cn0, >> + &bcm_sn0, >> + &bcm_sn1, >> + &bcm_sn2, >> +}; >> + >> +static struct qcom_icc_node *system_noc_nodes[] = { >> + [MASTER_AUDIO] = &qhm_audio, >> + [MASTER_GIC_AHB] = &qhm_gic, >> + [MASTER_PCIE_RSCC] = &qhm_pcie_rscc, >> + [MASTER_QDSS_BAM] = &qhm_qdss_bam, >> + [MASTER_QPIC] = &qhm_qpic, >> + [MASTER_QUP_0] = &qhm_qup0, >> + [MASTER_ANOC_SNOC] = &qnm_aggre_noc, >> + [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, >> + [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, >> + [MASTER_SNOC_CFG] = &qnm_system_noc_cfg, >> + [MASTER_PCIE_ANOC_CFG] = &qnm_system_noc_pcie_cfg, >> + [MASTER_CRYPTO] = &qxm_crypto, >> + [MASTER_IPA] = &qxm_ipa, >> + [MASTER_MVMSS] = &qxm_mvmss, >> + [MASTER_EMAC_0] = &xm_emac_0, >> + [MASTER_EMAC_1] = &xm_emac_1, >> + [MASTER_QDSS_ETR] = &xm_qdss_etr0, >> + [MASTER_QDSS_ETR_1] = &xm_qdss_etr1, >> + [MASTER_SDCC_1] = &xm_sdc1, >> + [MASTER_SDCC_4] = &xm_sdc4, >> + [MASTER_USB3_0] = &xm_usb3, >> + [SLAVE_ETH0_CFG] = &ps_eth0_cfg, >> + [SLAVE_ETH1_CFG] = &ps_eth1_cfg, >> + [SLAVE_AUDIO] = &qhs_audio, >> + [SLAVE_CLK_CTL] = &qhs_clk_ctl, >> + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto_cfg, >> + [SLAVE_IMEM_CFG] = &qhs_imem_cfg, >> + [SLAVE_IPA_CFG] = &qhs_ipa, >> + [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, >> + [SLAVE_CNOC_MSS] = &qhs_mss_cfg, >> + [SLAVE_ICBDI_MVMSS_CFG] = &qhs_mvmss_cfg, >> + [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, >> + [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, >> + [SLAVE_PCIE_2_CFG] = &qhs_pcie2_cfg, >> + [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rscc, >> + [SLAVE_PDM] = &qhs_pdm, >> + [SLAVE_PRNG] = &qhs_prng, >> + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, >> + [SLAVE_QPIC] = &qhs_qpic, >> + [SLAVE_QUP_0] = &qhs_qup0, >> + [SLAVE_SDCC_1] = &qhs_sdc1, >> + [SLAVE_SDCC_4] = &qhs_sdc4, >> + [SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex, >> + [SLAVE_TCSR] = &qhs_tcsr, >> + [SLAVE_TLMM] = &qhs_tlmm, >> + [SLAVE_USB3] = &qhs_usb3, >> + [SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy, >> + [SLAVE_A1NOC_CFG] = &qns_a1noc, >> + [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, >> + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, >> + [SLAVE_SNOC_CFG] = &qns_system_noc_cfg, >> + [SLAVE_PCIE_ANOC_CFG] = &qns_system_noc_pcie_cfg, >> + [SLAVE_IMEM] = &qxs_imem, >> + [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_system_noc, >> + [SLAVE_SERVICE_SNOC] = &srvc_system_noc, >> + [SLAVE_PCIE_0] = &xs_pcie_0, >> + [SLAVE_PCIE_1] = &xs_pcie_1, >> + [SLAVE_PCIE_2] = &xs_pcie_2, >> + [SLAVE_QDSS_STM] = &xs_qdss_stm, >> + [SLAVE_TCU] = &xs_sys_tcu_cfg, >> +}; >> + >> +static struct qcom_icc_desc sdx75_system_noc = { > Come on... we fixed it. > > There could be more issues because you used old file as template. Start > from scratch from new file. > > Best regards, > Krzysztof >