| Message ID | e793056e610ee8cfe2a8d69605402cd2445a517a.1693933849.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/dsc: cleanups | expand |
> Subject: [PATCH 4/8] drm/i915/dsc: rename pps write to intel_dsc_pps_write() > > Make the function name conform to existing style better. > LGTM. Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> > Cc: Suraj Kandpal <suraj.kandpal@intel.com> > Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++++++++++------------ > 1 file changed, 16 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c > b/drivers/gpu/drm/i915/display/intel_vdsc.c > index b0be6615a865..4086dbb25ca5 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -389,8 +389,8 @@ static void intel_dsc_get_pps_reg(const struct > intel_crtc_state *crtc_state, int > dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS(pipe, pps) : > DSCA_PPS(pps); } > > -static void intel_dsc_write_pps_reg(const struct intel_crtc_state *crtc_state, > - int pps, u32 pps_val) > +static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state, > + int pps, u32 pps_val) > { > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > struct drm_i915_private *i915 = to_i915(crtc->base.dev); @@ -443,41 > +443,41 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state > *crtc_state) > if (vdsc_cfg->vbr_enable) > pps_val |= DSC_VBR_ENABLE; > drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val); > - intel_dsc_write_pps_reg(crtc_state, 0, pps_val); > + intel_dsc_pps_write(crtc_state, 0, pps_val); > > /* Populate PICTURE_PARAMETER_SET_1 registers */ > pps_val = 0; > pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); > drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val); > - intel_dsc_write_pps_reg(crtc_state, 1, pps_val); > + intel_dsc_pps_write(crtc_state, 1, pps_val); > > /* Populate PICTURE_PARAMETER_SET_2 registers */ > pps_val = 0; > pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | > DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); > drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val); > - intel_dsc_write_pps_reg(crtc_state, 2, pps_val); > + intel_dsc_pps_write(crtc_state, 2, pps_val); > > /* Populate PICTURE_PARAMETER_SET_3 registers */ > pps_val = 0; > pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | > DSC_SLICE_WIDTH(vdsc_cfg->slice_width); > drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val); > - intel_dsc_write_pps_reg(crtc_state, 3, pps_val); > + intel_dsc_pps_write(crtc_state, 3, pps_val); > > /* Populate PICTURE_PARAMETER_SET_4 registers */ > pps_val = 0; > pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | > DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); > drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val); > - intel_dsc_write_pps_reg(crtc_state, 4, pps_val); > + intel_dsc_pps_write(crtc_state, 4, pps_val); > > /* Populate PICTURE_PARAMETER_SET_5 registers */ > pps_val = 0; > pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | > DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); > drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val); > - intel_dsc_write_pps_reg(crtc_state, 5, pps_val); > + intel_dsc_pps_write(crtc_state, 5, pps_val); > > /* Populate PICTURE_PARAMETER_SET_6 registers */ > pps_val = 0; > @@ -486,28 +486,28 @@ static void intel_dsc_pps_configure(const struct > intel_crtc_state *crtc_state) > DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | > DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); > drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val); > - intel_dsc_write_pps_reg(crtc_state, 6, pps_val); > + intel_dsc_pps_write(crtc_state, 6, pps_val); > > /* Populate PICTURE_PARAMETER_SET_7 registers */ > pps_val = 0; > pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | > DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); > drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val); > - intel_dsc_write_pps_reg(crtc_state, 7, pps_val); > + intel_dsc_pps_write(crtc_state, 7, pps_val); > > /* Populate PICTURE_PARAMETER_SET_8 registers */ > pps_val = 0; > pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | > DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); > drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val); > - intel_dsc_write_pps_reg(crtc_state, 8, pps_val); > + intel_dsc_pps_write(crtc_state, 8, pps_val); > > /* Populate PICTURE_PARAMETER_SET_9 registers */ > pps_val = 0; > pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | > DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); > drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); > - intel_dsc_write_pps_reg(crtc_state, 9, pps_val); > + intel_dsc_pps_write(crtc_state, 9, pps_val); > > /* Populate PICTURE_PARAMETER_SET_10 registers */ > pps_val = 0; > @@ -516,7 +516,7 @@ static void intel_dsc_pps_configure(const struct > intel_crtc_state *crtc_state) > DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) > | > > DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); > drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val); > - intel_dsc_write_pps_reg(crtc_state, 10, pps_val); > + intel_dsc_pps_write(crtc_state, 10, pps_val); > > /* Populate Picture parameter set 16 */ > pps_val = 0; > @@ -526,21 +526,21 @@ static void intel_dsc_pps_configure(const struct > intel_crtc_state *crtc_state) > DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / > vdsc_cfg->slice_height); > drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val); > - intel_dsc_write_pps_reg(crtc_state, 16, pps_val); > + intel_dsc_pps_write(crtc_state, 16, pps_val); > > if (DISPLAY_VER(dev_priv) >= 14) { > /* Populate PICTURE_PARAMETER_SET_17 registers */ > pps_val = 0; > pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg- > >second_line_bpg_offset); > drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val); > - intel_dsc_write_pps_reg(crtc_state, 17, pps_val); > + intel_dsc_pps_write(crtc_state, 17, pps_val); > > /* Populate PICTURE_PARAMETER_SET_18 registers */ > pps_val = 0; > pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) | > DSC_SL_OFFSET_ADJ(vdsc_cfg- > >second_line_offset_adj); > drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val); > - intel_dsc_write_pps_reg(crtc_state, 18, pps_val); > + intel_dsc_pps_write(crtc_state, 18, pps_val); > } > > /* Populate the RC_BUF_THRESH registers */ > -- > 2.39.2
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index b0be6615a865..4086dbb25ca5 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -389,8 +389,8 @@ static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS(pipe, pps) : DSCA_PPS(pps); } -static void intel_dsc_write_pps_reg(const struct intel_crtc_state *crtc_state, - int pps, u32 pps_val) +static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state, + int pps, u32 pps_val) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); @@ -443,41 +443,41 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) if (vdsc_cfg->vbr_enable) pps_val |= DSC_VBR_ENABLE; drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 0, pps_val); + intel_dsc_pps_write(crtc_state, 0, pps_val); /* Populate PICTURE_PARAMETER_SET_1 registers */ pps_val = 0; pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 1, pps_val); + intel_dsc_pps_write(crtc_state, 1, pps_val); /* Populate PICTURE_PARAMETER_SET_2 registers */ pps_val = 0; pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 2, pps_val); + intel_dsc_pps_write(crtc_state, 2, pps_val); /* Populate PICTURE_PARAMETER_SET_3 registers */ pps_val = 0; pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | DSC_SLICE_WIDTH(vdsc_cfg->slice_width); drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 3, pps_val); + intel_dsc_pps_write(crtc_state, 3, pps_val); /* Populate PICTURE_PARAMETER_SET_4 registers */ pps_val = 0; pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 4, pps_val); + intel_dsc_pps_write(crtc_state, 4, pps_val); /* Populate PICTURE_PARAMETER_SET_5 registers */ pps_val = 0; pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 5, pps_val); + intel_dsc_pps_write(crtc_state, 5, pps_val); /* Populate PICTURE_PARAMETER_SET_6 registers */ pps_val = 0; @@ -486,28 +486,28 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 6, pps_val); + intel_dsc_pps_write(crtc_state, 6, pps_val); /* Populate PICTURE_PARAMETER_SET_7 registers */ pps_val = 0; pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 7, pps_val); + intel_dsc_pps_write(crtc_state, 7, pps_val); /* Populate PICTURE_PARAMETER_SET_8 registers */ pps_val = 0; pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 8, pps_val); + intel_dsc_pps_write(crtc_state, 8, pps_val); /* Populate PICTURE_PARAMETER_SET_9 registers */ pps_val = 0; pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 9, pps_val); + intel_dsc_pps_write(crtc_state, 9, pps_val); /* Populate PICTURE_PARAMETER_SET_10 registers */ pps_val = 0; @@ -516,7 +516,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 10, pps_val); + intel_dsc_pps_write(crtc_state, 10, pps_val); /* Populate Picture parameter set 16 */ pps_val = 0; @@ -526,21 +526,21 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / vdsc_cfg->slice_height); drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 16, pps_val); + intel_dsc_pps_write(crtc_state, 16, pps_val); if (DISPLAY_VER(dev_priv) >= 14) { /* Populate PICTURE_PARAMETER_SET_17 registers */ pps_val = 0; pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset); drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 17, pps_val); + intel_dsc_pps_write(crtc_state, 17, pps_val); /* Populate PICTURE_PARAMETER_SET_18 registers */ pps_val = 0; pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) | DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj); drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 18, pps_val); + intel_dsc_pps_write(crtc_state, 18, pps_val); } /* Populate the RC_BUF_THRESH registers */
Make the function name conform to existing style better. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++++++++++------------ 1 file changed, 16 insertions(+), 16 deletions(-)