| Message ID | 915970973ef117fc8d47fbc57e8fa296235ad3e3.1693933849.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/dsc: cleanups | expand |
> Subject: [PATCH 6/8] drm/i915/dsc: clean up pps comments > > Unify comments to be the simple "PPS n" instead of all sorts of variants. > LGTM. Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> > Cc: Suraj Kandpal <suraj.kandpal@intel.com> > Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_vdsc.c | 56 +++++++++---------- > .../gpu/drm/i915/display/intel_vdsc_regs.h | 29 +++++----- > 2 files changed, 42 insertions(+), 43 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c > b/drivers/gpu/drm/i915/display/intel_vdsc.c > index 73bfa4d6633d..4855514d7b09 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -422,7 +422,7 @@ static void intel_dsc_pps_configure(const struct > intel_crtc_state *crtc_state) > int num_vdsc_instances = > intel_dsc_get_num_vdsc_instances(crtc_state); > int vdsc_instances_per_pipe = > intel_dsc_get_vdsc_per_pipe(crtc_state); > > - /* Populate PICTURE_PARAMETER_SET_0 registers */ > + /* PPS 0 */ > pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << > DSC_VER_MIN_SHIFT | > vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | @@ - > 445,36 +445,36 @@ static void intel_dsc_pps_configure(const struct > intel_crtc_state *crtc_state) > drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val); > intel_dsc_pps_write(crtc_state, 0, pps_val); > > - /* Populate PICTURE_PARAMETER_SET_1 registers */ > + /* PPS 1 */ > pps_val = DSC_BPP(vdsc_cfg->bits_per_pixel); > drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val); > intel_dsc_pps_write(crtc_state, 1, pps_val); > > - /* Populate PICTURE_PARAMETER_SET_2 registers */ > + /* PPS 2 */ > pps_val = DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | > DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); > drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val); > intel_dsc_pps_write(crtc_state, 2, pps_val); > > - /* Populate PICTURE_PARAMETER_SET_3 registers */ > + /* PPS 3 */ > pps_val = DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | > DSC_SLICE_WIDTH(vdsc_cfg->slice_width); > drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val); > intel_dsc_pps_write(crtc_state, 3, pps_val); > > - /* Populate PICTURE_PARAMETER_SET_4 registers */ > + /* PPS 4 */ > pps_val = DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | > DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); > drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val); > intel_dsc_pps_write(crtc_state, 4, pps_val); > > - /* Populate PICTURE_PARAMETER_SET_5 registers */ > + /* PPS 5 */ > pps_val = DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | > DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); > drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val); > intel_dsc_pps_write(crtc_state, 5, pps_val); > > - /* Populate PICTURE_PARAMETER_SET_6 registers */ > + /* PPS 6 */ > pps_val = DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | > DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) > | > DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | @@ - > 482,25 +482,25 @@ static void intel_dsc_pps_configure(const struct > intel_crtc_state *crtc_state) > drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val); > intel_dsc_pps_write(crtc_state, 6, pps_val); > > - /* Populate PICTURE_PARAMETER_SET_7 registers */ > + /* PPS 7 */ > pps_val = DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | > DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); > drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val); > intel_dsc_pps_write(crtc_state, 7, pps_val); > > - /* Populate PICTURE_PARAMETER_SET_8 registers */ > + /* PPS 8 */ > pps_val = DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | > DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); > drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val); > intel_dsc_pps_write(crtc_state, 8, pps_val); > > - /* Populate PICTURE_PARAMETER_SET_9 registers */ > + /* PPS 9 */ > pps_val = DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | > DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); > drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); > intel_dsc_pps_write(crtc_state, 9, pps_val); > > - /* Populate PICTURE_PARAMETER_SET_10 registers */ > + /* PPS 10 */ > pps_val = DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg- > >rc_quant_incr_limit0) | > DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) > | > DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) > | @@ -508,7 +508,7 @@ static void intel_dsc_pps_configure(const struct > intel_crtc_state *crtc_state) > drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val); > intel_dsc_pps_write(crtc_state, 10, pps_val); > > - /* Populate Picture parameter set 16 */ > + /* PPS 16 */ > pps_val = DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | > DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / > num_vdsc_instances) / > vdsc_cfg->slice_width) | > @@ -518,12 +518,12 @@ static void intel_dsc_pps_configure(const struct > intel_crtc_state *crtc_state) > intel_dsc_pps_write(crtc_state, 16, pps_val); > > if (DISPLAY_VER(dev_priv) >= 14) { > - /* Populate PICTURE_PARAMETER_SET_17 registers */ > + /* PPS 17 */ > pps_val = DSC_SL_BPG_OFFSET(vdsc_cfg- > >second_line_bpg_offset); > drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val); > intel_dsc_pps_write(crtc_state, 17, pps_val); > > - /* Populate PICTURE_PARAMETER_SET_18 registers */ > + /* PPS 18 */ > pps_val = DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) | > DSC_SL_OFFSET_ADJ(vdsc_cfg- > >second_line_offset_adj); > drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val); > @@ -854,7 +854,7 @@ static void intel_dsc_get_pps_config(struct > intel_crtc_state *crtc_state) > int num_vdsc_instances = > intel_dsc_get_num_vdsc_instances(crtc_state); > u32 pps_temp; > > - /* PPS_0 */ > + /* PPS 0 */ > pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0); > > vdsc_cfg->bits_per_component = (pps_temp & DSC_BPC_MASK) >> > DSC_BPC_SHIFT; @@ -867,7 +867,7 @@ static void > intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) > vdsc_cfg->native_420 = pps_temp & DSC_NATIVE_420_ENABLE; > vdsc_cfg->vbr_enable = pps_temp & DSC_VBR_ENABLE; > > - /* PPS_1 */ > + /* PPS 1 */ > pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1); > > vdsc_cfg->bits_per_pixel = pps_temp; > @@ -877,31 +877,31 @@ static void intel_dsc_get_pps_config(struct > intel_crtc_state *crtc_state) > > crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; > > - /* PPS_2 */ > + /* PPS 2 */ > pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2); > > vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PIC_WIDTH_MASK, > pps_temp) / num_vdsc_instances; > vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PIC_HEIGHT_MASK, > pps_temp); > > - /* PPS_3 */ > + /* PPS 3 */ > pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3); > > vdsc_cfg->slice_width = REG_FIELD_GET(DSC_SLICE_WIDTH_MASK, > pps_temp); > vdsc_cfg->slice_height = REG_FIELD_GET(DSC_SLICE_HEIGHT_MASK, > pps_temp); > > - /* PPS_4 */ > + /* PPS 4 */ > pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4); > > vdsc_cfg->initial_dec_delay = > REG_FIELD_GET(DSC_INITIAL_DEC_DELAY_MASK, pps_temp); > vdsc_cfg->initial_xmit_delay = > REG_FIELD_GET(DSC_INITIAL_XMIT_DELAY_MASK, pps_temp); > > - /* PPS_5 */ > + /* PPS 5 */ > pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5); > > vdsc_cfg->scale_decrement_interval = > REG_FIELD_GET(DSC_SCALE_DEC_INT_MASK, pps_temp); > vdsc_cfg->scale_increment_interval = > REG_FIELD_GET(DSC_SCALE_INC_INT_MASK, pps_temp); > > - /* PPS_6 */ > + /* PPS 6 */ > pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6); > > vdsc_cfg->initial_scale_value = > REG_FIELD_GET(DSC_INITIAL_SCALE_VALUE_MASK, pps_temp); @@ -909,41 > +909,41 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state > *crtc_state) > vdsc_cfg->flatness_min_qp = > REG_FIELD_GET(DSC_FLATNESS_MIN_QP_MASK, pps_temp); > vdsc_cfg->flatness_max_qp = > REG_FIELD_GET(DSC_FLATNESS_MAX_QP_MASK, pps_temp); > > - /* PPS_7 */ > + /* PPS 7 */ > pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7); > > vdsc_cfg->nfl_bpg_offset = > REG_FIELD_GET(DSC_NFL_BPG_OFFSET_MASK, pps_temp); > vdsc_cfg->slice_bpg_offset = > REG_FIELD_GET(DSC_SLICE_BPG_OFFSET_MASK, pps_temp); > > - /* PPS_8 */ > + /* PPS 8 */ > pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8); > > vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_INITIAL_OFFSET_MASK, > pps_temp); > vdsc_cfg->final_offset = REG_FIELD_GET(DSC_FINAL_OFFSET_MASK, > pps_temp); > > - /* PPS_9 */ > + /* PPS 9 */ > pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9); > > vdsc_cfg->rc_model_size = > REG_FIELD_GET(DSC_RC_MODEL_SIZE_MASK, pps_temp); > > - /* PPS_10 */ > + /* PPS 10 */ > pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10); > > vdsc_cfg->rc_quant_incr_limit0 = > REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT0_MASK, pps_temp); > vdsc_cfg->rc_quant_incr_limit1 = > REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT1_MASK, pps_temp); > > - /* PPS_16 */ > + /* PPS 16 */ > pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16); > > vdsc_cfg->slice_chunk_size = > REG_FIELD_GET(DSC_SLICE_CHUNK_SIZE_MASK, pps_temp); > > if (DISPLAY_VER(i915) >= 14) { > - /* PPS_17 */ > + /* PPS 17 */ > pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17); > > vdsc_cfg->second_line_bpg_offset = > REG_FIELD_GET(DSC_SL_BPG_OFFSET_MASK, pps_temp); > > - /* PPS_18 */ > + /* PPS 18 */ > pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18); > > vdsc_cfg->nsl_bpg_offset = > REG_FIELD_GET(DSC_NSL_BPG_OFFSET_MASK, pps_temp); diff --git > a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h > b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h > index 5cbcbd9db7b1..58d282dcfc6f 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h > @@ -72,7 +72,7 @@ > #define ICL_DSC0_PPS(pipe, pps) > _MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4)) > #define ICL_DSC1_PPS(pipe, pps) > _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4)) > > -/* PPS0 */ > +/* PPS 0 */ > #define DSC_NATIVE_422_ENABLE BIT(23) > #define DSC_NATIVE_420_ENABLE BIT(22) > #define DSC_ALT_ICH_SEL (1 << 20) > @@ -87,22 +87,22 @@ > #define DSC_VER_MIN_SHIFT 4 > #define DSC_VER_MAJ (0x1 << 0) > > -/* PPS1 */ > +/* PPS 1 */ > #define DSC_BPP(bpp) ((bpp) << 0) > > -/* PPS2 */ > +/* PPS 2 */ > #define DSC_PIC_WIDTH_MASK REG_GENMASK(31, 16) > #define DSC_PIC_HEIGHT_MASK REG_GENMASK(15, 0) > #define DSC_PIC_WIDTH(pic_width) > REG_FIELD_PREP(DSC_PIC_WIDTH_MASK, pic_width) > #define DSC_PIC_HEIGHT(pic_height) > REG_FIELD_PREP(DSC_PIC_HEIGHT_MASK, pic_height) > > -/* PPS3 */ > +/* PPS 3 */ > #define DSC_SLICE_WIDTH_MASK REG_GENMASK(31, > 16) > #define DSC_SLICE_HEIGHT_MASK REG_GENMASK(15, 0) > #define DSC_SLICE_WIDTH(slice_width) > REG_FIELD_PREP(DSC_SLICE_WIDTH_MASK, slice_width) > #define DSC_SLICE_HEIGHT(slice_height) > REG_FIELD_PREP(DSC_SLICE_HEIGHT_MASK, slice_height) > > -/* PPS4 */ > +/* PPS 4 */ > #define DSC_INITIAL_DEC_DELAY_MASK REG_GENMASK(31, > 16) > #define DSC_INITIAL_XMIT_DELAY_MASK REG_GENMASK(9, 0) > #define DSC_INITIAL_DEC_DELAY(dec_delay) > REG_FIELD_PREP(DSC_INITIAL_DEC_DELAY_MASK, \ > @@ -110,13 +110,13 @@ > #define DSC_INITIAL_XMIT_DELAY(xmit_delay) > REG_FIELD_PREP(DSC_INITIAL_XMIT_DELAY_MASK, \ > xmit_delay) > > -/* PPS5 */ > +/* PPS 5 */ > #define DSC_SCALE_DEC_INT_MASK REG_GENMASK(27, > 16) > #define DSC_SCALE_INC_INT_MASK REG_GENMASK(15, 0) > #define DSC_SCALE_DEC_INT(scale_dec) > REG_FIELD_PREP(DSC_SCALE_DEC_INT_MASK, scale_dec) > #define DSC_SCALE_INC_INT(scale_inc) > REG_FIELD_PREP(DSC_SCALE_INC_INT_MASK, scale_inc) > > -/* PPS6 */ > +/* PPS 6 */ > #define DSC_FLATNESS_MAX_QP_MASK REG_GENMASK(28, > 24) > #define DSC_FLATNESS_MIN_QP_MASK REG_GENMASK(20, > 16) > #define DSC_FIRST_LINE_BPG_OFFSET_MASK REG_GENMASK(12, 8) > @@ -128,13 +128,13 @@ > #define DSC_INITIAL_SCALE_VALUE(value) > REG_FIELD_PREP(DSC_INITIAL_SCALE_VALUE_MASK, \ > value) > > -/* PPS7 */ > +/* PPS 7 */ > #define DSC_NFL_BPG_OFFSET_MASK REG_GENMASK(31, 16) > #define DSC_SLICE_BPG_OFFSET_MASK REG_GENMASK(15, 0) > #define DSC_NFL_BPG_OFFSET(bpg_offset) > REG_FIELD_PREP(DSC_NFL_BPG_OFFSET_MASK, bpg_offset) > #define DSC_SLICE_BPG_OFFSET(bpg_offset) > REG_FIELD_PREP(DSC_SLICE_BPG_OFFSET_MASK, \ > bpg_offset) > -/* PPS8 */ > +/* PPS 8 */ > #define DSC_INITIAL_OFFSET_MASK REG_GENMASK(31, 16) > #define DSC_FINAL_OFFSET_MASK REG_GENMASK(15, 0) > #define DSC_INITIAL_OFFSET(initial_offset) > REG_FIELD_PREP(DSC_INITIAL_OFFSET_MASK, \ > @@ -142,7 +142,7 @@ > #define DSC_FINAL_OFFSET(final_offset) > REG_FIELD_PREP(DSC_FINAL_OFFSET_MASK, \ > final_offset) > > -/* PPS9 */ > +/* PPS 9 */ > #define DSC_RC_EDGE_FACTOR_MASK REG_GENMASK(19, 16) > #define DSC_RC_MODEL_SIZE_MASK REG_GENMASK(15, 0) > #define DSC_RC_EDGE_FACTOR(rc_edge_fact) > REG_FIELD_PREP(DSC_RC_EDGE_FACTOR_MASK, \ > @@ -150,7 +150,7 @@ > #define DSC_RC_MODEL_SIZE(rc_model_size) > REG_FIELD_PREP(DSC_RC_MODEL_SIZE_MASK, \ > rc_model_size) > > -/* PPS10 */ > +/* PPS 10 */ > #define DSC_RC_TGT_OFF_LOW_MASK > REG_GENMASK(23, 20) > #define DSC_RC_TGT_OFF_HIGH_MASK > REG_GENMASK(19, 16) > #define DSC_RC_QUANT_INC_LIMIT1_MASK > REG_GENMASK(12, 8) > @@ -162,7 +162,7 @@ > #define DSC_RC_QUANT_INC_LIMIT1(lim) > REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT1_MASK, lim) > #define DSC_RC_QUANT_INC_LIMIT0(lim) > REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT0_MASK, lim) > > -/* PPS16 */ > +/* PPS 16 */ > #define DSC_SLICE_ROW_PR_FRME_MASK > REG_GENMASK(31, 20) > #define DSC_SLICE_PER_LINE_MASK REG_GENMASK(18, > 16) > #define DSC_SLICE_CHUNK_SIZE_MASK > REG_GENMASK(15, 0) > @@ -173,12 +173,11 @@ > #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) > REG_FIELD_PREP(DSC_SLICE_CHUNK_SIZE_MASK, \ > > slice_chunk_size) > > -/* MTL Display Stream Compression registers */ > -/* PPS17 */ > +/* PPS 17 (MTL+) */ > #define DSC_SL_BPG_OFFSET_MASK REG_GENMASK(31, > 27) > #define DSC_SL_BPG_OFFSET(offset) > REG_FIELD_PREP(DSC_SL_BPG_OFFSET_MASK, offset) > > -/* PPS18 */ > +/* PPS 18 (MTL+) */ > #define DSC_NSL_BPG_OFFSET_MASK REG_GENMASK(31, > 16) > #define DSC_SL_OFFSET_ADJ_MASK REG_GENMASK(15, 0) > #define DSC_NSL_BPG_OFFSET(offset) > REG_FIELD_PREP(DSC_NSL_BPG_OFFSET_MASK, offset) > -- > 2.39.2
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 73bfa4d6633d..4855514d7b09 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -422,7 +422,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); - /* Populate PICTURE_PARAMETER_SET_0 registers */ + /* PPS 0 */ pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << DSC_VER_MIN_SHIFT | vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | @@ -445,36 +445,36 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 0, pps_val); - /* Populate PICTURE_PARAMETER_SET_1 registers */ + /* PPS 1 */ pps_val = DSC_BPP(vdsc_cfg->bits_per_pixel); drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 1, pps_val); - /* Populate PICTURE_PARAMETER_SET_2 registers */ + /* PPS 2 */ pps_val = DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 2, pps_val); - /* Populate PICTURE_PARAMETER_SET_3 registers */ + /* PPS 3 */ pps_val = DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | DSC_SLICE_WIDTH(vdsc_cfg->slice_width); drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 3, pps_val); - /* Populate PICTURE_PARAMETER_SET_4 registers */ + /* PPS 4 */ pps_val = DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 4, pps_val); - /* Populate PICTURE_PARAMETER_SET_5 registers */ + /* PPS 5 */ pps_val = DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 5, pps_val); - /* Populate PICTURE_PARAMETER_SET_6 registers */ + /* PPS 6 */ pps_val = DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | @@ -482,25 +482,25 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 6, pps_val); - /* Populate PICTURE_PARAMETER_SET_7 registers */ + /* PPS 7 */ pps_val = DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 7, pps_val); - /* Populate PICTURE_PARAMETER_SET_8 registers */ + /* PPS 8 */ pps_val = DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 8, pps_val); - /* Populate PICTURE_PARAMETER_SET_9 registers */ + /* PPS 9 */ pps_val = DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 9, pps_val); - /* Populate PICTURE_PARAMETER_SET_10 registers */ + /* PPS 10 */ pps_val = DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | @@ -508,7 +508,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 10, pps_val); - /* Populate Picture parameter set 16 */ + /* PPS 16 */ pps_val = DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / vdsc_cfg->slice_width) | @@ -518,12 +518,12 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) intel_dsc_pps_write(crtc_state, 16, pps_val); if (DISPLAY_VER(dev_priv) >= 14) { - /* Populate PICTURE_PARAMETER_SET_17 registers */ + /* PPS 17 */ pps_val = DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset); drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 17, pps_val); - /* Populate PICTURE_PARAMETER_SET_18 registers */ + /* PPS 18 */ pps_val = DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) | DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj); drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val); @@ -854,7 +854,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); u32 pps_temp; - /* PPS_0 */ + /* PPS 0 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0); vdsc_cfg->bits_per_component = (pps_temp & DSC_BPC_MASK) >> DSC_BPC_SHIFT; @@ -867,7 +867,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) vdsc_cfg->native_420 = pps_temp & DSC_NATIVE_420_ENABLE; vdsc_cfg->vbr_enable = pps_temp & DSC_VBR_ENABLE; - /* PPS_1 */ + /* PPS 1 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1); vdsc_cfg->bits_per_pixel = pps_temp; @@ -877,31 +877,31 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; - /* PPS_2 */ + /* PPS 2 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2); vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PIC_WIDTH_MASK, pps_temp) / num_vdsc_instances; vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PIC_HEIGHT_MASK, pps_temp); - /* PPS_3 */ + /* PPS 3 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3); vdsc_cfg->slice_width = REG_FIELD_GET(DSC_SLICE_WIDTH_MASK, pps_temp); vdsc_cfg->slice_height = REG_FIELD_GET(DSC_SLICE_HEIGHT_MASK, pps_temp); - /* PPS_4 */ + /* PPS 4 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4); vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_INITIAL_DEC_DELAY_MASK, pps_temp); vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_INITIAL_XMIT_DELAY_MASK, pps_temp); - /* PPS_5 */ + /* PPS 5 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5); vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_SCALE_DEC_INT_MASK, pps_temp); vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_SCALE_INC_INT_MASK, pps_temp); - /* PPS_6 */ + /* PPS 6 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6); vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_INITIAL_SCALE_VALUE_MASK, pps_temp); @@ -909,41 +909,41 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_FLATNESS_MIN_QP_MASK, pps_temp); vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_FLATNESS_MAX_QP_MASK, pps_temp); - /* PPS_7 */ + /* PPS 7 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7); vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_NFL_BPG_OFFSET_MASK, pps_temp); vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_SLICE_BPG_OFFSET_MASK, pps_temp); - /* PPS_8 */ + /* PPS 8 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8); vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_INITIAL_OFFSET_MASK, pps_temp); vdsc_cfg->final_offset = REG_FIELD_GET(DSC_FINAL_OFFSET_MASK, pps_temp); - /* PPS_9 */ + /* PPS 9 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9); vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_RC_MODEL_SIZE_MASK, pps_temp); - /* PPS_10 */ + /* PPS 10 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10); vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT0_MASK, pps_temp); vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT1_MASK, pps_temp); - /* PPS_16 */ + /* PPS 16 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16); vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_SLICE_CHUNK_SIZE_MASK, pps_temp); if (DISPLAY_VER(i915) >= 14) { - /* PPS_17 */ + /* PPS 17 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17); vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_SL_BPG_OFFSET_MASK, pps_temp); - /* PPS_18 */ + /* PPS 18 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18); vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_NSL_BPG_OFFSET_MASK, pps_temp); diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index 5cbcbd9db7b1..58d282dcfc6f 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -72,7 +72,7 @@ #define ICL_DSC0_PPS(pipe, pps) _MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4)) #define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4)) -/* PPS0 */ +/* PPS 0 */ #define DSC_NATIVE_422_ENABLE BIT(23) #define DSC_NATIVE_420_ENABLE BIT(22) #define DSC_ALT_ICH_SEL (1 << 20) @@ -87,22 +87,22 @@ #define DSC_VER_MIN_SHIFT 4 #define DSC_VER_MAJ (0x1 << 0) -/* PPS1 */ +/* PPS 1 */ #define DSC_BPP(bpp) ((bpp) << 0) -/* PPS2 */ +/* PPS 2 */ #define DSC_PIC_WIDTH_MASK REG_GENMASK(31, 16) #define DSC_PIC_HEIGHT_MASK REG_GENMASK(15, 0) #define DSC_PIC_WIDTH(pic_width) REG_FIELD_PREP(DSC_PIC_WIDTH_MASK, pic_width) #define DSC_PIC_HEIGHT(pic_height) REG_FIELD_PREP(DSC_PIC_HEIGHT_MASK, pic_height) -/* PPS3 */ +/* PPS 3 */ #define DSC_SLICE_WIDTH_MASK REG_GENMASK(31, 16) #define DSC_SLICE_HEIGHT_MASK REG_GENMASK(15, 0) #define DSC_SLICE_WIDTH(slice_width) REG_FIELD_PREP(DSC_SLICE_WIDTH_MASK, slice_width) #define DSC_SLICE_HEIGHT(slice_height) REG_FIELD_PREP(DSC_SLICE_HEIGHT_MASK, slice_height) -/* PPS4 */ +/* PPS 4 */ #define DSC_INITIAL_DEC_DELAY_MASK REG_GENMASK(31, 16) #define DSC_INITIAL_XMIT_DELAY_MASK REG_GENMASK(9, 0) #define DSC_INITIAL_DEC_DELAY(dec_delay) REG_FIELD_PREP(DSC_INITIAL_DEC_DELAY_MASK, \ @@ -110,13 +110,13 @@ #define DSC_INITIAL_XMIT_DELAY(xmit_delay) REG_FIELD_PREP(DSC_INITIAL_XMIT_DELAY_MASK, \ xmit_delay) -/* PPS5 */ +/* PPS 5 */ #define DSC_SCALE_DEC_INT_MASK REG_GENMASK(27, 16) #define DSC_SCALE_INC_INT_MASK REG_GENMASK(15, 0) #define DSC_SCALE_DEC_INT(scale_dec) REG_FIELD_PREP(DSC_SCALE_DEC_INT_MASK, scale_dec) #define DSC_SCALE_INC_INT(scale_inc) REG_FIELD_PREP(DSC_SCALE_INC_INT_MASK, scale_inc) -/* PPS6 */ +/* PPS 6 */ #define DSC_FLATNESS_MAX_QP_MASK REG_GENMASK(28, 24) #define DSC_FLATNESS_MIN_QP_MASK REG_GENMASK(20, 16) #define DSC_FIRST_LINE_BPG_OFFSET_MASK REG_GENMASK(12, 8) @@ -128,13 +128,13 @@ #define DSC_INITIAL_SCALE_VALUE(value) REG_FIELD_PREP(DSC_INITIAL_SCALE_VALUE_MASK, \ value) -/* PPS7 */ +/* PPS 7 */ #define DSC_NFL_BPG_OFFSET_MASK REG_GENMASK(31, 16) #define DSC_SLICE_BPG_OFFSET_MASK REG_GENMASK(15, 0) #define DSC_NFL_BPG_OFFSET(bpg_offset) REG_FIELD_PREP(DSC_NFL_BPG_OFFSET_MASK, bpg_offset) #define DSC_SLICE_BPG_OFFSET(bpg_offset) REG_FIELD_PREP(DSC_SLICE_BPG_OFFSET_MASK, \ bpg_offset) -/* PPS8 */ +/* PPS 8 */ #define DSC_INITIAL_OFFSET_MASK REG_GENMASK(31, 16) #define DSC_FINAL_OFFSET_MASK REG_GENMASK(15, 0) #define DSC_INITIAL_OFFSET(initial_offset) REG_FIELD_PREP(DSC_INITIAL_OFFSET_MASK, \ @@ -142,7 +142,7 @@ #define DSC_FINAL_OFFSET(final_offset) REG_FIELD_PREP(DSC_FINAL_OFFSET_MASK, \ final_offset) -/* PPS9 */ +/* PPS 9 */ #define DSC_RC_EDGE_FACTOR_MASK REG_GENMASK(19, 16) #define DSC_RC_MODEL_SIZE_MASK REG_GENMASK(15, 0) #define DSC_RC_EDGE_FACTOR(rc_edge_fact) REG_FIELD_PREP(DSC_RC_EDGE_FACTOR_MASK, \ @@ -150,7 +150,7 @@ #define DSC_RC_MODEL_SIZE(rc_model_size) REG_FIELD_PREP(DSC_RC_MODEL_SIZE_MASK, \ rc_model_size) -/* PPS10 */ +/* PPS 10 */ #define DSC_RC_TGT_OFF_LOW_MASK REG_GENMASK(23, 20) #define DSC_RC_TGT_OFF_HIGH_MASK REG_GENMASK(19, 16) #define DSC_RC_QUANT_INC_LIMIT1_MASK REG_GENMASK(12, 8) @@ -162,7 +162,7 @@ #define DSC_RC_QUANT_INC_LIMIT1(lim) REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT1_MASK, lim) #define DSC_RC_QUANT_INC_LIMIT0(lim) REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT0_MASK, lim) -/* PPS16 */ +/* PPS 16 */ #define DSC_SLICE_ROW_PR_FRME_MASK REG_GENMASK(31, 20) #define DSC_SLICE_PER_LINE_MASK REG_GENMASK(18, 16) #define DSC_SLICE_CHUNK_SIZE_MASK REG_GENMASK(15, 0) @@ -173,12 +173,11 @@ #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) REG_FIELD_PREP(DSC_SLICE_CHUNK_SIZE_MASK, \ slice_chunk_size) -/* MTL Display Stream Compression registers */ -/* PPS17 */ +/* PPS 17 (MTL+) */ #define DSC_SL_BPG_OFFSET_MASK REG_GENMASK(31, 27) #define DSC_SL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_SL_BPG_OFFSET_MASK, offset) -/* PPS18 */ +/* PPS 18 (MTL+) */ #define DSC_NSL_BPG_OFFSET_MASK REG_GENMASK(31, 16) #define DSC_SL_OFFSET_ADJ_MASK REG_GENMASK(15, 0) #define DSC_NSL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_NSL_BPG_OFFSET_MASK, offset)
Unify comments to be the simple "PPS n" instead of all sorts of variants. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_vdsc.c | 56 +++++++++---------- .../gpu/drm/i915/display/intel_vdsc_regs.h | 29 +++++----- 2 files changed, 42 insertions(+), 43 deletions(-)