diff mbox series

[1/2] drm/i915: Split gt cache flushing and gt idling functions

Message ID 20230905193614.69771-2-andi.shyti@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series Drop caches per GT | expand

Commit Message

Andi Shyti Sept. 5, 2023, 7:36 p.m. UTC 
In preparation for multi-gt cache flushing debugfs interface,
split the cache dropping function and gt idling.

Based on a patch by Tvrtko.

Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 32 +++++++++++++++++++++--------
 1 file changed, 24 insertions(+), 8 deletions(-)

Comments

Nirmoy Das Sept. 7, 2023, 9:04 a.m. UTC | #1 
On 9/5/2023 9:36 PM, Andi Shyti wrote:
> In preparation for multi-gt cache flushing debugfs interface,
> split the cache dropping function and gt idling.
>
> Based on a patch by Tvrtko.
>
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_debugfs.c | 32 +++++++++++++++++++++--------
>   1 file changed, 24 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 7a90a2e32c9f1..3dfe8a8b7cdfe 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -703,11 +703,25 @@ i915_drop_caches_get(void *data, u64 *val)
>   	return 0;
>   }
>   
> +static int gt_idle(struct intel_gt *gt, u64 val)
> +{
> +	if (val & (DROP_RETIRE | DROP_IDLE))
> +		intel_gt_retire_requests(gt);
> +
> +	if (val & DROP_IDLE) {
> +		int ret;
> +
> +		ret = intel_gt_pm_wait_for_idle(gt);
return intel_gt_pm_wait_for_idle(gt) should work fine.
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return 0;
> +}
> +
>   static int
>   gt_drop_caches(struct intel_gt *gt, u64 val)
>   {
> -	int ret;
> -
>   	if (val & DROP_RESET_ACTIVE &&
>   	    wait_for(intel_engines_are_idle(gt), 200))
>   		intel_gt_set_wedged(gt);
> @@ -716,13 +730,9 @@ gt_drop_caches(struct intel_gt *gt, u64 val)
>   		intel_gt_retire_requests(gt);
>   
>   	if (val & (DROP_IDLE | DROP_ACTIVE)) {
> -		ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT);
> -		if (ret)
> -			return ret;
> -	}
> +		int ret;
>   
> -	if (val & DROP_IDLE) {
> -		ret = intel_gt_pm_wait_for_idle(gt);
> +		ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT);
>   		if (ret)
>   			return ret;
>   	}
> @@ -746,10 +756,16 @@ i915_drop_caches_set(void *data, u64 val)
>   	drm_dbg(&i915->drm, "Dropping caches: 0x%08llx [0x%08llx]\n",
>   		val, val & DROP_ALL);
>   
> +	/* Flush all the active requests across both GT ... */
For now it is just GT0 so this comment should be in next patch ?
>   	ret = gt_drop_caches(to_gt(i915), val);
>   	if (ret)
>   		return ret;
>   
> +	/* ... then wait for idle as there may be cross-gt wakerefs. */

same as above.

Regards,

Nirmoy

> +	ret = gt_idle(to_gt(i915), val);
> +	if (ret)
> +		return ret;
> +
>   	fs_reclaim_acquire(GFP_KERNEL);
>   	flags = memalloc_noreclaim_save();
>   	if (val & DROP_BOUND)
Andi Shyti Sept. 7, 2023, 9:57 a.m. UTC | #2 
Hi Nirmoy,

please ignore this series... I'm going to send Tvrtko's original
work. The changes in patch 1 are not required.

Thank you!
Andi

On Thu, Sep 07, 2023 at 11:04:33AM +0200, Nirmoy Das wrote:
> 
> On 9/5/2023 9:36 PM, Andi Shyti wrote:
> > In preparation for multi-gt cache flushing debugfs interface,
> > split the cache dropping function and gt idling.
> > 
> > Based on a patch by Tvrtko.
> > 
> > Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_debugfs.c | 32 +++++++++++++++++++++--------
> >   1 file changed, 24 insertions(+), 8 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 7a90a2e32c9f1..3dfe8a8b7cdfe 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -703,11 +703,25 @@ i915_drop_caches_get(void *data, u64 *val)
> >   	return 0;
> >   }
> > +static int gt_idle(struct intel_gt *gt, u64 val)
> > +{
> > +	if (val & (DROP_RETIRE | DROP_IDLE))
> > +		intel_gt_retire_requests(gt);
> > +
> > +	if (val & DROP_IDLE) {
> > +		int ret;
> > +
> > +		ret = intel_gt_pm_wait_for_idle(gt);
> return intel_gt_pm_wait_for_idle(gt) should work fine.
> > +		if (ret)
> > +			return ret;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> >   static int
> >   gt_drop_caches(struct intel_gt *gt, u64 val)
> >   {
> > -	int ret;
> > -
> >   	if (val & DROP_RESET_ACTIVE &&
> >   	    wait_for(intel_engines_are_idle(gt), 200))
> >   		intel_gt_set_wedged(gt);
> > @@ -716,13 +730,9 @@ gt_drop_caches(struct intel_gt *gt, u64 val)
> >   		intel_gt_retire_requests(gt);
> >   	if (val & (DROP_IDLE | DROP_ACTIVE)) {
> > -		ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT);
> > -		if (ret)
> > -			return ret;
> > -	}
> > +		int ret;
> > -	if (val & DROP_IDLE) {
> > -		ret = intel_gt_pm_wait_for_idle(gt);
> > +		ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT);
> >   		if (ret)
> >   			return ret;
> >   	}
> > @@ -746,10 +756,16 @@ i915_drop_caches_set(void *data, u64 val)
> >   	drm_dbg(&i915->drm, "Dropping caches: 0x%08llx [0x%08llx]\n",
> >   		val, val & DROP_ALL);
> > +	/* Flush all the active requests across both GT ... */
> For now it is just GT0 so this comment should be in next patch ?
> >   	ret = gt_drop_caches(to_gt(i915), val);
> >   	if (ret)
> >   		return ret;
> > +	/* ... then wait for idle as there may be cross-gt wakerefs. */
> 
> same as above.
> 
> Regards,
> 
> Nirmoy
> 
> > +	ret = gt_idle(to_gt(i915), val);
> > +	if (ret)
> > +		return ret;
> > +
> >   	fs_reclaim_acquire(GFP_KERNEL);
> >   	flags = memalloc_noreclaim_save();
> >   	if (val & DROP_BOUND)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 7a90a2e32c9f1..3dfe8a8b7cdfe 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -703,11 +703,25 @@  i915_drop_caches_get(void *data, u64 *val)
 	return 0;
 }
 
+static int gt_idle(struct intel_gt *gt, u64 val)
+{
+	if (val & (DROP_RETIRE | DROP_IDLE))
+		intel_gt_retire_requests(gt);
+
+	if (val & DROP_IDLE) {
+		int ret;
+
+		ret = intel_gt_pm_wait_for_idle(gt);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
 static int
 gt_drop_caches(struct intel_gt *gt, u64 val)
 {
-	int ret;
-
 	if (val & DROP_RESET_ACTIVE &&
 	    wait_for(intel_engines_are_idle(gt), 200))
 		intel_gt_set_wedged(gt);
@@ -716,13 +730,9 @@  gt_drop_caches(struct intel_gt *gt, u64 val)
 		intel_gt_retire_requests(gt);
 
 	if (val & (DROP_IDLE | DROP_ACTIVE)) {
-		ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT);
-		if (ret)
-			return ret;
-	}
+		int ret;
 
-	if (val & DROP_IDLE) {
-		ret = intel_gt_pm_wait_for_idle(gt);
+		ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT);
 		if (ret)
 			return ret;
 	}
@@ -746,10 +756,16 @@  i915_drop_caches_set(void *data, u64 val)
 	drm_dbg(&i915->drm, "Dropping caches: 0x%08llx [0x%08llx]\n",
 		val, val & DROP_ALL);
 
+	/* Flush all the active requests across both GT ... */
 	ret = gt_drop_caches(to_gt(i915), val);
 	if (ret)
 		return ret;
 
+	/* ... then wait for idle as there may be cross-gt wakerefs. */
+	ret = gt_idle(to_gt(i915), val);
+	if (ret)
+		return ret;
+
 	fs_reclaim_acquire(GFP_KERNEL);
 	flags = memalloc_noreclaim_save();
 	if (val & DROP_BOUND)