Message ID | 543183ecfba929683c1b8d7ff24d75df489ef0cf.1693996662.git.quic_varada@quicinc.com (mailing list archive) |
---|---|
State | New, archived |
Delegated to: | viresh kumar |
Headers | show |
Series | Enable cpufreq for IPQ5332 & IPQ9574 | expand |
On 7.09.2023 07:21, Varadarajan Narayanan wrote: > The earlier 'l' value of 0x3e is for 1.5GHz. Not all SKUs support > this frequency. Hence set it to 0x2d to get 1.1GHz which is > supported in all SKUs. > > Fixes: c7ef7fbb1ccf ("clk: qcom: apss-ipq-pll: add support for IPQ5332") > Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
On Thu, 7 Sept 2023 at 08:22, Varadarajan Narayanan <quic_varada@quicinc.com> wrote: > > The earlier 'l' value of 0x3e is for 1.5GHz. Not all SKUs support > this frequency. Hence set it to 0x2d to get 1.1GHz which is > supported in all SKUs. > > Fixes: c7ef7fbb1ccf ("clk: qcom: apss-ipq-pll: add support for IPQ5332") > Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c index 18c4ffe..41279e5 100644 --- a/drivers/clk/qcom/apss-ipq-pll.c +++ b/drivers/clk/qcom/apss-ipq-pll.c @@ -74,7 +74,7 @@ static struct clk_alpha_pll ipq_pll_stromer_plus = { }; static const struct alpha_pll_config ipq5332_pll_config = { - .l = 0x3e, + .l = 0x2d, .config_ctl_val = 0x4001075b, .config_ctl_hi_val = 0x304, .main_output_mask = BIT(0),