| Message ID | 20230825124138.9088-1-ankita@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v8,1/1] vfio/nvgpu: Add vfio pci variant module for grace hopper | expand |
On Fri, 25 Aug 2023 05:41:38 -0700 <ankita@nvidia.com> wrote: > From: Ankit Agrawal <ankita@nvidia.com> > > NVIDIA's upcoming Grace Hopper Superchip provides a PCI-like device > for the on-chip GPU that is the logical OS representation of the > internal proprietary cache coherent interconnect. > > This representation has a number of limitations compared to a real PCI > device, in particular, it does not model the coherent GPU memory > aperture as a PCI config space BAR, and PCI doesn't know anything > about cacheable memory types. > > Provide a VFIO PCI variant driver that adapts the unique PCI > representation into a more standard PCI representation facing > userspace. The GPU memory aperture is obtained from ACPI using > device_property_read_u64(), according to the FW specification, > and exported to userspace as a separate VFIO_REGION. Since the device > implements only one 64-bit BAR (BAR0), the GPU memory aperture is mapped > to the next available PCI BAR (BAR2). Qemu will then naturally generate a > PCI device in the VM with two 64-bit BARs (where the cacheable aperture > reported in BAR2). > > Since this memory region is actually cache coherent with the CPU, the > VFIO variant driver will mmap it into VMA using a cacheable mapping. The > mapping is done using remap_pfn_range(). > > PCI BAR are aligned to the power-of-2, but the actual memory on the > device may not. A read or write access to the physical address from the > last device PFN up to the next power-of-2 aligned physical address > results in reading ~0 and dropped writes. > > This goes along with a qemu series to provides the necessary > implementation of the Grace Hopper Superchip firmware specification so > that the guest operating system can see the correct ACPI modeling for > the coherent GPU device. Verified with the CUDA workload in the VM. > https://www.mail-archive.com/qemu-devel@nongnu.org/msg967557.html > > This patch is split from a patch series being pursued separately: > https://lore.kernel.org/lkml/20230405180134.16932-1-ankita@nvidia.com/ > > Applied and tested over next-20230824. > > Signed-off-by: Ankit Agrawal <ankita@nvidia.com> > --- > > Link for v7: > https://lore.kernel.org/all/20230822202303.19661-1-ankita@nvidia.com/ > > v7 -> v8 > - Various field names updated. > - Added a new function to handle VFIO_DEVICE_GET_REGION_INFO ioctl. > - Locking protection for memremap to bar region and other changes > including overflow recommended in v7. > - Added code to fail if the devmem size advertized is 0 in system DSDT. A few trivial comments below, but I think more importantly we need resolution to Christoph's concern whether this driver should be considered for mainline. As Ankit identified earlier, there is a non-mainline, open source driver for this device, though we've never previously made any requirements regarding how the device is used by userspace. In fact we have a cdx bus now with vfio-cdx support, where I don't see any mainline drivers other than vfio-cdx. There does however appear to be DPDK support for cdx devices exposed through vfio. In this case we've created an infrastructure within vfio-pci to support device specific variant drivers. To date those drivers have only supported migration, but the door is certainly open for other device specific features. Even in the case of migration, the drivers are device specific and retrieve, store, and transmit device specific data as a blob. We've left IGD support in the base code for compatibility reasons, but I think we've agreed that similar device specific features would be done in variant drivers such as this. There's perhaps an argument whether userspace should compose this device itself, for example finding the firmware attributes in sysfs and directly mmap'ing the coherent memory via /dev/mem to back a virtual BAR or otherwise pass-through this associated region. We didn't require that from userspace for IGD (ie. the OpRegion and bridge config space) because we felt access to those regions (with appropriate permissions) was within the scope of providing usable access to the device, where QEMU would need effectively arbitrary permissions relative to a management tool to otherwise provide a usable device. I've previously raised the point whether the coherent region here might be exposed as a device specific region (such as we do for the above IGD regions) rather than a virtual BAR, but the NVIDIA folks feel strongly that the BAR approach is correct. Please continue the discussion, but I'm not seeing anything here that feels significantly different than what we created vfio-pci variant drivers to do. Also, for the team of reviewers for vfio-pci variant drivers, please have your say. If anything, I'm more concerned about the state of the userspace portion where the proposal referenced above has been shot down by QEMU because it tries to fundamentally change the VM machine based on this device being attached. I'd like to avoid another scenario like vaddr where the referenced use case fails to materialize in any generally usable way. [additional code comments below] Thanks, Alex > v6 -> v7 > - Handled out-of-bound and overflow conditions at various places to validate > input offset and length. > - Added code to return EINVAL for offset beyond region size. > > v5 -> v6 > - Added the code to handle BAR2 read/write using memremap to the device > memory. > > v4 -> v5 > - Changed the module name from nvgpu-vfio-pci to nvgrace-gpu-vfio-pci. > - Fixed memory leak and added suggested boundary checks on device memory > mapping. > - Added code to read all Fs and ignored write on region outside of the > physical memory. > - Other miscellaneous cleanup suggestions. > > v3 -> v4 > - Mapping the available device memory using sparse mmap. The region outside > the device memory is handled by read/write ops. > - Removed the fault handler added in v3. > > v2 -> v3 > - Added fault handler to map the region outside the physical GPU memory > up to the next power-of-2 to a dummy PFN. > - Changed to select instead of "depends on" VFIO_PCI_CORE for all the > vfio-pci variant driver. > - Code cleanup based on feedback comments. > - Code implemented and tested against v6.4-rc4. > > v1 -> v2 > - Updated the wording of reference to BAR offset and replaced with > index. > - The GPU memory is exposed at the fixed BAR2_REGION_INDEX. > - Code cleanup based on feedback comments. > > MAINTAINERS | 6 + > drivers/vfio/pci/Kconfig | 2 + > drivers/vfio/pci/Makefile | 2 + > drivers/vfio/pci/nvgrace-gpu/Kconfig | 10 + > drivers/vfio/pci/nvgrace-gpu/Makefile | 3 + > drivers/vfio/pci/nvgrace-gpu/main.c | 481 ++++++++++++++++++++++++++ > 6 files changed, 504 insertions(+) > create mode 100644 drivers/vfio/pci/nvgrace-gpu/Kconfig > create mode 100644 drivers/vfio/pci/nvgrace-gpu/Makefile > create mode 100644 drivers/vfio/pci/nvgrace-gpu/main.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 250c43c675cb..6042b09ad920 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -22638,6 +22638,12 @@ L: kvm@vger.kernel.org > S: Maintained > F: drivers/vfio/platform/ > > +VFIO NVIDIA GRACE GPU DRIVER > +M: Ankit Agrawal <ankita@nvidia.com> > +L: kvm@vger.kernel.org > +S: Maintained > +F: drivers/vfio/pci/nvgrace-gpu/ > + > VGA_SWITCHEROO > R: Lukas Wunner <lukas@wunner.de> > S: Maintained > diff --git a/drivers/vfio/pci/Kconfig b/drivers/vfio/pci/Kconfig > index 8125e5f37832..2456210e85f1 100644 > --- a/drivers/vfio/pci/Kconfig > +++ b/drivers/vfio/pci/Kconfig > @@ -65,4 +65,6 @@ source "drivers/vfio/pci/hisilicon/Kconfig" > > source "drivers/vfio/pci/pds/Kconfig" > > +source "drivers/vfio/pci/nvgrace-gpu/Kconfig" > + > endmenu > diff --git a/drivers/vfio/pci/Makefile b/drivers/vfio/pci/Makefile > index 45167be462d8..1352c65e568a 100644 > --- a/drivers/vfio/pci/Makefile > +++ b/drivers/vfio/pci/Makefile > @@ -13,3 +13,5 @@ obj-$(CONFIG_MLX5_VFIO_PCI) += mlx5/ > obj-$(CONFIG_HISI_ACC_VFIO_PCI) += hisilicon/ > > obj-$(CONFIG_PDS_VFIO_PCI) += pds/ > + > +obj-$(CONFIG_NVGRACE_GPU_VFIO_PCI) += nvgrace-gpu/ > diff --git a/drivers/vfio/pci/nvgrace-gpu/Kconfig b/drivers/vfio/pci/nvgrace-gpu/Kconfig > new file mode 100644 > index 000000000000..b46f2d97a1d6 > --- /dev/null > +++ b/drivers/vfio/pci/nvgrace-gpu/Kconfig > @@ -0,0 +1,10 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +config NVGRACE_GPU_VFIO_PCI > + tristate "VFIO support for the GPU in the NVIDIA Grace Hopper Superchip" > + depends on ARM64 || (COMPILE_TEST && 64BIT) > + select VFIO_PCI_CORE > + help > + VFIO support for the GPU in the NVIDIA Grace Hopper Superchip is > + required to assign the GPU device to a VM using KVM/qemu/etc. > + > + If you don't know what to do here, say N. > diff --git a/drivers/vfio/pci/nvgrace-gpu/Makefile b/drivers/vfio/pci/nvgrace-gpu/Makefile > new file mode 100644 > index 000000000000..3ca8c187897a > --- /dev/null > +++ b/drivers/vfio/pci/nvgrace-gpu/Makefile > @@ -0,0 +1,3 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +obj-$(CONFIG_NVGRACE_GPU_VFIO_PCI) += nvgrace-gpu-vfio-pci.o > +nvgrace-gpu-vfio-pci-y := main.o > diff --git a/drivers/vfio/pci/nvgrace-gpu/main.c b/drivers/vfio/pci/nvgrace-gpu/main.c > new file mode 100644 > index 000000000000..324547bc8ab2 > --- /dev/null > +++ b/drivers/vfio/pci/nvgrace-gpu/main.c > @@ -0,0 +1,481 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved > + */ > + > +#include <linux/pci.h> > +#include <linux/vfio_pci_core.h> > +#include <linux/vfio.h> > + > +struct nvgrace_gpu_vfio_pci_core_device { > + struct vfio_pci_core_device core_device; > + phys_addr_t memphys; > + size_t memlength; > + void *memmap; > + struct mutex memmap_lock; > +}; > + > +static int nvgrace_gpu_vfio_pci_open_device(struct vfio_device *core_vdev) > +{ > + struct vfio_pci_core_device *vdev = > + container_of(core_vdev, struct vfio_pci_core_device, vdev); > + struct nvgrace_gpu_vfio_pci_core_device *nvdev = container_of( > + core_vdev, struct nvgrace_gpu_vfio_pci_core_device, core_device.vdev); > + int ret; > + > + ret = vfio_pci_core_enable(vdev); > + if (ret) > + return ret; > + > + vfio_pci_core_finish_enable(vdev); > + > + mutex_init(&nvdev->memmap_lock); > + > + return 0; > +} > + > +static void nvgrace_gpu_vfio_pci_close_device(struct vfio_device *core_vdev) > +{ > + struct nvgrace_gpu_vfio_pci_core_device *nvdev = container_of( > + core_vdev, struct nvgrace_gpu_vfio_pci_core_device, core_device.vdev); > + > + if (nvdev->memmap) { > + memunmap(nvdev->memmap); > + nvdev->memmap = NULL; > + } > + > + mutex_destroy(&nvdev->memmap_lock); > + > + vfio_pci_core_close_device(core_vdev); > +} > + > +static int nvgrace_gpu_vfio_pci_mmap(struct vfio_device *core_vdev, > + struct vm_area_struct *vma) > +{ > + struct nvgrace_gpu_vfio_pci_core_device *nvdev = container_of( > + core_vdev, struct nvgrace_gpu_vfio_pci_core_device, core_device.vdev); > + > + unsigned long start_pfn; > + unsigned int index; > + u64 req_len, pgoff, end; > + int ret = 0; > + > + index = vma->vm_pgoff >> (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT); > + if (index != VFIO_PCI_BAR2_REGION_INDEX) > + return vfio_pci_core_mmap(core_vdev, vma); > + > + /* > + * Request to mmap the BAR. Map to the CPU accessible memory on the > + * GPU using the memory information gathered from the system ACPI > + * tables. > + */ > + pgoff = vma->vm_pgoff & > + ((1U << (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT)) - 1); > + > + if (check_sub_overflow(vma->vm_end, vma->vm_start, &req_len) || > + check_add_overflow(PHYS_PFN(nvdev->memphys), pgoff, &start_pfn) || > + check_add_overflow(PFN_PHYS(pgoff), req_len, &end)) > + return -EOVERFLOW; > + > + /* > + * Check that the mapping request does not go beyond available device > + * memory size > + */ > + if (end > nvdev->memlength) > + return -EINVAL; > + > + /* > + * Perform a PFN map to the memory and back the device BAR by the > + * GPU memory. > + * > + * The available GPU memory size may not be power-of-2 aligned. Given > + * that the memory is exposed as a BAR, the mapping request is of the > + * power-of-2 aligned size. Map only up to the size of the GPU memory. > + * If the memory access is beyond the actual GPU memory size, it will > + * be handled by the vfio_device_ops read/write. > + * > + * During device reset, the GPU is safely disconnected to the CPU > + * and access to the BAR will be immediately returned preventing > + * machine check. > + */ > + ret = remap_pfn_range(vma, vma->vm_start, start_pfn, > + req_len, vma->vm_page_prot); > + if (ret) > + return ret; > + > + vma->vm_pgoff = start_pfn; > + > + return 0; > +} > + > +static long > +nvgrace_gpu_vfio_pci_ioctl_get_region_info(struct vfio_device *core_vdev, > + unsigned long arg) > +{ > + unsigned long minsz = offsetofend(struct vfio_region_info, offset); > + struct nvgrace_gpu_vfio_pci_core_device *nvdev = container_of( > + core_vdev, struct nvgrace_gpu_vfio_pci_core_device, core_device.vdev); > + struct vfio_region_info info; > + > + if (copy_from_user(&info, (void __user *)arg, minsz)) > + return -EFAULT; > + > + if (info.argsz < minsz) > + return -EINVAL; > + > + if (info.index == VFIO_PCI_BAR2_REGION_INDEX) { > + /* > + * Request to determine the BAR region information. Send the > + * GPU memory information. > + */ > + uint32_t size; > + int ret; > + struct vfio_region_info_cap_sparse_mmap *sparse; > + struct vfio_info_cap caps = { .buf = NULL, .size = 0 }; > + > + size = struct_size(sparse, areas, 1); > + > + /* > + * Setup for sparse mapping for the device memory. Only the > + * available device memory on the hardware is shown as a > + * mappable region. > + */ > + sparse = kzalloc(size, GFP_KERNEL); > + if (!sparse) > + return -ENOMEM; > + > + sparse->nr_areas = 1; > + sparse->areas[0].offset = 0; > + sparse->areas[0].size = nvdev->memlength; > + sparse->header.id = VFIO_REGION_INFO_CAP_SPARSE_MMAP; > + sparse->header.version = 1; > + > + ret = vfio_info_add_capability(&caps, &sparse->header, size); > + kfree(sparse); > + if (ret) > + return ret; > + > + info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); > + /* > + * The available GPU memory size may not be power-of-2 aligned. > + * Given that the memory is exposed as a BAR and may not be > + * aligned, roundup to the next power-of-2. > + */ > + info.size = roundup_pow_of_two(nvdev->memlength); > + info.flags = VFIO_REGION_INFO_FLAG_READ | > + VFIO_REGION_INFO_FLAG_WRITE | > + VFIO_REGION_INFO_FLAG_MMAP; > + > + if (caps.size) { > + info.flags |= VFIO_REGION_INFO_FLAG_CAPS; > + if (info.argsz < sizeof(info) + caps.size) { > + info.argsz = sizeof(info) + caps.size; > + info.cap_offset = 0; > + } else { > + vfio_info_cap_shift(&caps, sizeof(info)); > + if (copy_to_user((void __user *)arg + > + sizeof(info), caps.buf, > + caps.size)) { > + kfree(caps.buf); > + return -EFAULT; > + } > + info.cap_offset = sizeof(info); > + } > + kfree(caps.buf); > + } > + return copy_to_user((void __user *)arg, &info, minsz) ? > + -EFAULT : 0; > + } > + return vfio_pci_core_ioctl(core_vdev, VFIO_DEVICE_GET_REGION_INFO, arg); > +} > + > +static long nvgrace_gpu_vfio_pci_ioctl(struct vfio_device *core_vdev, > + unsigned int cmd, unsigned long arg) > +{ > + if (cmd == VFIO_DEVICE_GET_REGION_INFO) > + return nvgrace_gpu_vfio_pci_ioctl_get_region_info(core_vdev, arg); > + > + return vfio_pci_core_ioctl(core_vdev, cmd, arg); > +} > + > +/* > + * Read count bytes from the device memory at an offset. The actual device > + * memory size (available) may not be a power-of-2. So the driver fakes > + * the size to a power-of-2 (reported) when exposing to a user space driver. > + * > + * Read request beyond the actual device size is filled with ~0, while > + * those beyond the actual reported size is skipped. > + * > + * A read from a negative or a reported+ offset, a negative count are > + * considered error conditions and returned with an -EINVAL. > + */ > +ssize_t nvgrace_gpu_read_mem(void __user *buf, size_t count, loff_t *ppos, > + struct nvgrace_gpu_vfio_pci_core_device *nvdev) > +{ > + u64 offset = *ppos & VFIO_PCI_OFFSET_MASK; > + size_t mem_count, i, bar_size = roundup_pow_of_two(nvdev->memlength); > + u8 val = 0xFF; > + > + if (offset >= bar_size) > + return -EINVAL; > + > + /* Clip short the read request beyond reported BAR size */ > + count = min(count, bar_size - (size_t)offset); > + > + /* > + * Determine how many bytes to be actually read from the device memory. > + * Do not read from the offset beyond available size. > + */ > + if (offset >= nvdev->memlength) > + mem_count = 0; > + else > + mem_count = min(count, nvdev->memlength - (size_t)offset); > + > + /* > + * Handle read on the BAR2 region. Map to the target device memory > + * physical address and copy to the request read buffer. > + */ > + if (copy_to_user(buf, (u8 *)nvdev->memmap + offset, mem_count)) > + return -EFAULT; > + > + /* > + * Only the device memory present on the hardware is mapped, which may > + * not be power-of-2 aligned. A read to the BAR2 region implies an > + * access outside the available device memory on the hardware. Fill > + * such read request with ~0. > + */ > + for (i = mem_count; i < count; i++) > + put_user(val, (unsigned char __user *)(buf + i)); > + > + return count; > +} > + > +static ssize_t nvgrace_gpu_vfio_pci_read(struct vfio_device *core_vdev, > + char __user *buf, size_t count, loff_t *ppos) > +{ > + unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); > + struct nvgrace_gpu_vfio_pci_core_device *nvdev = container_of( > + core_vdev, struct nvgrace_gpu_vfio_pci_core_device, core_device.vdev); > + > + if (index == VFIO_PCI_BAR2_REGION_INDEX) { > + mutex_lock(&nvdev->memmap_lock); > + if (!nvdev->memmap) { > + nvdev->memmap = memremap(nvdev->memphys, nvdev->memlength, MEMREMAP_WB); > + if (!nvdev->memmap) { > + mutex_unlock(&nvdev->memmap_lock); > + return -ENOMEM; > + } > + } > + mutex_unlock(&nvdev->memmap_lock); > + > + return nvgrace_gpu_read_mem(buf, count, ppos, nvdev); > + } > + > + return vfio_pci_core_read(core_vdev, buf, count, ppos); > +} > + > +/* > + * Write count bytes to the device memory at a given offset. The actual device > + * memory size (available) may not be a power-of-2. So the driver fakes the > + * size to a power-of-2 (reported) when exposing to a user space driver. > + * > + * Write request beyond the actual device size are dropped, while those > + * beyond the actual reported size are skipped entirely. > + * > + * A write to a negative or a reported+ offset, a negative count are > + * considered error conditions and returned with an -EINVAL. > + */ > +ssize_t nvgrace_gpu_write_mem(size_t count, loff_t *ppos, const void __user *buf, > + struct nvgrace_gpu_vfio_pci_core_device *nvdev) > +{ > + u64 offset = *ppos & VFIO_PCI_OFFSET_MASK; > + size_t mem_count, bar_size = roundup_pow_of_two(nvdev->memlength); > + > + if (offset >= bar_size) > + return -EINVAL; > + > + /* Clip short the read request beyond reported BAR size */ > + count = min(count, bar_size - (size_t)offset); > + > + /* > + * Determine how many bytes to be actually written to the device memory. > + * Do not write to the offset beyond available size. > + */ > + if (offset >= nvdev->memlength) > + mem_count = 0; We could simply 'return count;' here, then setting mem_count doesn't need to be behind the 'else'. > + else > + mem_count = min(count, nvdev->memlength - (size_t)offset); > + > + /* > + * Only the device memory present on the hardware is mapped, which may > + * not be power-of-2 aligned. A write to the BAR2 region implies an > + * access outside the available device memory on the hardware. Drop > + * those write requests. > + */ > + if (copy_from_user((u8 *)nvdev->memmap + offset, buf, mem_count)) > + return -EFAULT; > + > + return count; > +} > + > +static ssize_t nvgrace_gpu_vfio_pci_write(struct vfio_device *core_vdev, > + const char __user *buf, size_t count, loff_t *ppos) > +{ > + unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); > + struct nvgrace_gpu_vfio_pci_core_device *nvdev = container_of( > + core_vdev, struct nvgrace_gpu_vfio_pci_core_device, core_device.vdev); > + > + if (index == VFIO_PCI_BAR2_REGION_INDEX) { > + mutex_lock(&nvdev->memmap_lock); > + if (!nvdev->memmap) { > + nvdev->memmap = memremap(nvdev->memphys, nvdev->memlength, MEMREMAP_WB); > + if (!nvdev->memmap) { > + mutex_unlock(&nvdev->memmap_lock); > + return -ENOMEM; > + } > + } > + mutex_unlock(&nvdev->memmap_lock); > + > + return nvgrace_gpu_write_mem(count, ppos, buf, nvdev); > + } > + > + return vfio_pci_core_write(core_vdev, buf, count, ppos); > +} > + > +static const struct vfio_device_ops nvgrace_gpu_vfio_pci_ops = { > + .name = "nvgrace-gpu-vfio-pci", > + .init = vfio_pci_core_init_dev, > + .release = vfio_pci_core_release_dev, > + .open_device = nvgrace_gpu_vfio_pci_open_device, > + .close_device = nvgrace_gpu_vfio_pci_close_device, > + .ioctl = nvgrace_gpu_vfio_pci_ioctl, > + .read = nvgrace_gpu_vfio_pci_read, > + .write = nvgrace_gpu_vfio_pci_write, > + .mmap = nvgrace_gpu_vfio_pci_mmap, > + .request = vfio_pci_core_request, > + .match = vfio_pci_core_match, > + .bind_iommufd = vfio_iommufd_physical_bind, > + .unbind_iommufd = vfio_iommufd_physical_unbind, > + .attach_ioas = vfio_iommufd_physical_attach_ioas, > +}; > + > +static struct > +nvgrace_gpu_vfio_pci_core_device *nvgrace_gpu_drvdata(struct pci_dev *pdev) > +{ > + struct vfio_pci_core_device *core_device = dev_get_drvdata(&pdev->dev); > + > + return container_of(core_device, struct nvgrace_gpu_vfio_pci_core_device, > + core_device); > +} > + > +static int > +nvgrace_gpu_vfio_pci_fetch_memory_property(struct pci_dev *pdev, > + struct nvgrace_gpu_vfio_pci_core_device *nvdev) > +{ > + int ret; > + u64 memphys, memlength; > + > + /* > + * The memory information is present in the system ACPI tables as DSD > + * properties nvidia,gpu-mem-base-pa and nvidia,gpu-mem-size. > + */ > + ret = device_property_read_u64(&pdev->dev, "nvidia,gpu-mem-base-pa", > + &(memphys)); > + if (ret) > + goto done; > + > + if (memphys > type_max(phys_addr_t)) { > + ret = -EOVERFLOW; > + goto done; > + } > + > + nvdev->memphys = memphys; > + > + ret = device_property_read_u64(&pdev->dev, "nvidia,gpu-mem-size", > + &(memlength)); > + if (ret) > + goto done; > + > + if (memlength > type_max(size_t)) { > + ret = -EOVERFLOW; > + goto done; > + } > + > + /* > + * If the C2C link is not up due to an error, the coherent device > + * memory size is returned as 0. Fail in such case. > + */ > + if (memlength == 0) { > + ret = -ENOMEM; > + goto done; > + } > + > + nvdev->memlength = memlength; > + > +done: > + return ret; Without needing to release a lock or perform any other sort of cleanup, I'm not sure why we need a common exit path, each of the above could simply call 'return ret;' or 'return -ERRNO;'. > +} > + > +static int nvgrace_gpu_vfio_pci_probe(struct pci_dev *pdev, > + const struct pci_device_id *id) > +{ > + struct nvgrace_gpu_vfio_pci_core_device *nvdev; > + int ret; > + > + nvdev = vfio_alloc_device(nvgrace_gpu_vfio_pci_core_device, core_device.vdev, > + &pdev->dev, &nvgrace_gpu_vfio_pci_ops); > + if (IS_ERR(nvdev)) > + return PTR_ERR(nvdev); > + > + dev_set_drvdata(&pdev->dev, nvdev); > + > + ret = nvgrace_gpu_vfio_pci_fetch_memory_property(pdev, nvdev); > + if (ret) > + goto out_put_vdev; > + > + ret = vfio_pci_core_register_device(&nvdev->core_device); > + if (ret) > + goto out_put_vdev; > + > + return ret; > + > +out_put_vdev: > + vfio_put_device(&nvdev->core_device.vdev); > + return ret; > +} > + > +static void nvgrace_gpu_vfio_pci_remove(struct pci_dev *pdev) > +{ > + struct nvgrace_gpu_vfio_pci_core_device *nvdev = nvgrace_gpu_drvdata(pdev); > + struct vfio_pci_core_device *vdev = &nvdev->core_device; > + > + vfio_pci_core_unregister_device(vdev); > + vfio_put_device(&vdev->vdev); > +} > + > +static const struct pci_device_id nvgrace_gpu_vfio_pci_table[] = { > + /* GH200 120GB */ > + { PCI_DRIVER_OVERRIDE_DEVICE_VFIO(PCI_VENDOR_ID_NVIDIA, 0x2342) }, > + /* GH200 480GB */ > + { PCI_DRIVER_OVERRIDE_DEVICE_VFIO(PCI_VENDOR_ID_NVIDIA, 0x2345) }, > + {} > +}; > + > +MODULE_DEVICE_TABLE(pci, nvgrace_gpu_vfio_pci_table); > + > +static struct pci_driver nvgrace_gpu_vfio_pci_driver = { > + .name = KBUILD_MODNAME, > + .id_table = nvgrace_gpu_vfio_pci_table, > + .probe = nvgrace_gpu_vfio_pci_probe, > + .remove = nvgrace_gpu_vfio_pci_remove, > + .err_handler = &vfio_pci_core_err_handlers, > + .driver_managed_dma = true, > +}; > + > +module_pci_driver(nvgrace_gpu_vfio_pci_driver); > + > +MODULE_LICENSE("GPL v2"); > +MODULE_AUTHOR("Ankit Agrawal <ankita@nvidia.com>"); > +MODULE_AUTHOR("Aniket Agashe <aniketa@nvidia.com>"); I think we should probably have a Signed-off-by or Acked-by from Aniket to add them as an author. > +MODULE_DESCRIPTION( > + "VFIO NVGRACE GPU PF - User Level driver for NVIDIA devices with CPU coherently accessible device memory");
On Thu, Sep 07, 2023 at 01:55:46PM -0600, Alex Williamson wrote: > There's perhaps an argument whether userspace should compose this > device itself, for example finding the firmware attributes in sysfs and > directly mmap'ing the coherent memory via /dev/mem to back a virtual > BAR or otherwise pass-through this associated region. I don't think this works, secure boot turns off /dev/mem and other things that would let you do this AFAIK. > I've previously raised the point whether the coherent region here > might be exposed as a device specific region (such as we do for the > above IGD regions) rather than a virtual BAR, but the NVIDIA folks feel > strongly that the BAR approach is correct. I think it really depends on what the qemu side wants to do.. > Please continue the discussion, but I'm not seeing anything here that > feels significantly different than what we created vfio-pci variant > drivers to do. Right, the driver seems fine for what the infrastructure was created to do. Jason
On Thu, 7 Sep 2023 21:34:41 -0300 Jason Gunthorpe <jgg@nvidia.com> wrote: > On Thu, Sep 07, 2023 at 01:55:46PM -0600, Alex Williamson wrote: > > > There's perhaps an argument whether userspace should compose this > > device itself, for example finding the firmware attributes in sysfs and > > directly mmap'ing the coherent memory via /dev/mem to back a virtual > > BAR or otherwise pass-through this associated region. > > I don't think this works, secure boot turns off /dev/mem and other > things that would let you do this AFAIK. Yep, it's got issues, just trying to play devil's advocate for a non-kernel approach. > > I've previously raised the point whether the coherent region here > > might be exposed as a device specific region (such as we do for the > > above IGD regions) rather than a virtual BAR, but the NVIDIA folks feel > > strongly that the BAR approach is correct. > > I think it really depends on what the qemu side wants to do.. Ok, I thought you had been one of the proponents of the fake BAR approach as more resembling CXL. Do we need to reevaluate that the tinkering with the VM machine topology and firmware tables would better align to a device specific region that QEMU inserts into the VM address space so that bare metal and virtual machine versions of this device look more similar? Thanks, Alex
On Thu, Sep 07, 2023 at 10:04:10PM -0600, Alex Williamson wrote: > > I think it really depends on what the qemu side wants to do.. > > Ok, I thought you had been one of the proponents of the fake BAR > approach as more resembling CXL. Do we need to reevaluate that the > tinkering with the VM machine topology and firmware tables would better > align to a device specific region that QEMU inserts into the VM address > space so that bare metal and virtual machine versions of this device > look more similar? Thanks, Yes, providing something to a VM that doesn't look anything like the underlying hardware feels pretty strange.
On Fri, Sep 08, 2023 at 01:50:36AM -0700, Christoph Hellwig wrote: > On Thu, Sep 07, 2023 at 10:04:10PM -0600, Alex Williamson wrote: > > > I think it really depends on what the qemu side wants to do.. > > > > Ok, I thought you had been one of the proponents of the fake BAR > > approach as more resembling CXL. Yes, I do prefer this because it is ultimately simpler on the qemu and VM side. This ACPI tinkering is not nice. > > Do we need to reevaluate that the tinkering with the VM machine > > topology and firmware tables would better align to a device > > specific region that QEMU inserts into the VM address space so > > that bare metal and virtual machine versions of this device look > > more similar? Thanks, > Yes, providing something to a VM that doesn't look anything like the > underlying hardware feels pretty strange. I don't see the goal as perfect emulation of the real HW. Aiming for minimally disruptive to the ecosystem to support this quirky pre-CXL HW. Perfect emulation would need a unique VFIO uAPI and more complex qemu changes, and it really brings nothing of value. Jason
> From: Jason Gunthorpe <jgg@nvidia.com> > Sent: Friday, September 8, 2023 8:16 PM > > On Fri, Sep 08, 2023 at 01:50:36AM -0700, Christoph Hellwig wrote: > > On Thu, Sep 07, 2023 at 10:04:10PM -0600, Alex Williamson wrote: > > > > I think it really depends on what the qemu side wants to do.. > > > > > > Ok, I thought you had been one of the proponents of the fake BAR > > > approach as more resembling CXL. > > Yes, I do prefer this because it is ultimately simpler on the qemu and > VM side. This ACPI tinkering is not nice. > > > > Do we need to reevaluate that the tinkering with the VM machine > > > topology and firmware tables would better align to a device > > > specific region that QEMU inserts into the VM address space so > > > that bare metal and virtual machine versions of this device look > > > more similar? Thanks, > > > Yes, providing something to a VM that doesn't look anything like the > > underlying hardware feels pretty strange. > > I don't see the goal as perfect emulation of the real HW. > > Aiming for minimally disruptive to the ecosystem to support this > quirky pre-CXL HW. > > Perfect emulation would need a unique VFIO uAPI and more complex qemu > changes, and it really brings nothing of value. > Does it mean that this requires maintaining a new guest driver different from the existing one on bare metal?
>> I don't see the goal as perfect emulation of the real HW. >> >> Aiming for minimally disruptive to the ecosystem to support this >> quirky pre-CXL HW. >> >> Perfect emulation would need a unique VFIO uAPI and more complex qemu >> changes, and it really brings nothing of value. >> > > Does it mean that this requires maintaining a new guest driver > different from the existing one on bare metal? No, the VM would use the same Nvidia open source driver that is used by the bare metal. (https://github.com/NVIDIA/open-gpu-kernel-modules).
> From: Ankit Agrawal <ankita@nvidia.com> > Sent: Monday, September 11, 2023 4:18 PM > > >> I don't see the goal as perfect emulation of the real HW. > >> > >> Aiming for minimally disruptive to the ecosystem to support this > >> quirky pre-CXL HW. > >> > >> Perfect emulation would need a unique VFIO uAPI and more complex > qemu > >> changes, and it really brings nothing of value. > >> > > > > Does it mean that this requires maintaining a new guest driver > > different from the existing one on bare metal? > > No, the VM would use the same Nvidia open source driver that is used by the > bare metal. (https://github.com/NVIDIA/open-gpu-kernel-modules). because this driver already supports two ways of accessing the aperture: one via the firmware table, the other using this fake BAR2?
>> > Does it mean that this requires maintaining a new guest driver >> > different from the existing one on bare metal? >> >> No, the VM would use the same Nvidia open source driver that is used by the >> bare metal. (https://github.com/NVIDIA/open-gpu-kernel-modules). > > because this driver already supports two ways of accessing the aperture: > one via the firmware table, the other using this fake BAR2? Yes, exactly. The driver supports both ways. An absence of ACPI DSD device property describing the device memory (that happens for the virtualization case) when Qemu does not expose them via VM ACPI) provides an indication to the driver that it needs to use the fake BAR (and determine the memory properties from it); use the memory region otherwise.
diff --git a/MAINTAINERS b/MAINTAINERS index 250c43c675cb..6042b09ad920 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22638,6 +22638,12 @@ L: kvm@vger.kernel.org S: Maintained F: drivers/vfio/platform/ +VFIO NVIDIA GRACE GPU DRIVER +M: Ankit Agrawal <ankita@nvidia.com> +L: kvm@vger.kernel.org +S: Maintained +F: drivers/vfio/pci/nvgrace-gpu/ + VGA_SWITCHEROO R: Lukas Wunner <lukas@wunner.de> S: Maintained diff --git a/drivers/vfio/pci/Kconfig b/drivers/vfio/pci/Kconfig index 8125e5f37832..2456210e85f1 100644 --- a/drivers/vfio/pci/Kconfig +++ b/drivers/vfio/pci/Kconfig @@ -65,4 +65,6 @@ source "drivers/vfio/pci/hisilicon/Kconfig" source "drivers/vfio/pci/pds/Kconfig" +source "drivers/vfio/pci/nvgrace-gpu/Kconfig" + endmenu diff --git a/drivers/vfio/pci/Makefile b/drivers/vfio/pci/Makefile index 45167be462d8..1352c65e568a 100644 --- a/drivers/vfio/pci/Makefile +++ b/drivers/vfio/pci/Makefile @@ -13,3 +13,5 @@ obj-$(CONFIG_MLX5_VFIO_PCI) += mlx5/ obj-$(CONFIG_HISI_ACC_VFIO_PCI) += hisilicon/ obj-$(CONFIG_PDS_VFIO_PCI) += pds/ + +obj-$(CONFIG_NVGRACE_GPU_VFIO_PCI) += nvgrace-gpu/ diff --git a/drivers/vfio/pci/nvgrace-gpu/Kconfig b/drivers/vfio/pci/nvgrace-gpu/Kconfig new file mode 100644 index 000000000000..b46f2d97a1d6 --- /dev/null +++ b/drivers/vfio/pci/nvgrace-gpu/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only +config NVGRACE_GPU_VFIO_PCI + tristate "VFIO support for the GPU in the NVIDIA Grace Hopper Superchip" + depends on ARM64 || (COMPILE_TEST && 64BIT) + select VFIO_PCI_CORE + help + VFIO support for the GPU in the NVIDIA Grace Hopper Superchip is + required to assign the GPU device to a VM using KVM/qemu/etc. + + If you don't know what to do here, say N. diff --git a/drivers/vfio/pci/nvgrace-gpu/Makefile b/drivers/vfio/pci/nvgrace-gpu/Makefile new file mode 100644 index 000000000000..3ca8c187897a --- /dev/null +++ b/drivers/vfio/pci/nvgrace-gpu/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_NVGRACE_GPU_VFIO_PCI) += nvgrace-gpu-vfio-pci.o +nvgrace-gpu-vfio-pci-y := main.o diff --git a/drivers/vfio/pci/nvgrace-gpu/main.c b/drivers/vfio/pci/nvgrace-gpu/main.c new file mode 100644 index 000000000000..324547bc8ab2 --- /dev/null +++ b/drivers/vfio/pci/nvgrace-gpu/main.c @@ -0,0 +1,481 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved + */ + +#include <linux/pci.h> +#include <linux/vfio_pci_core.h> +#include <linux/vfio.h> + +struct nvgrace_gpu_vfio_pci_core_device { + struct vfio_pci_core_device core_device; + phys_addr_t memphys; + size_t memlength; + void *memmap; + struct mutex memmap_lock; +}; + +static int nvgrace_gpu_vfio_pci_open_device(struct vfio_device *core_vdev) +{ + struct vfio_pci_core_device *vdev = + container_of(core_vdev, struct vfio_pci_core_device, vdev); + struct nvgrace_gpu_vfio_pci_core_device *nvdev = container_of( + core_vdev, struct nvgrace_gpu_vfio_pci_core_device, core_device.vdev); + int ret; + + ret = vfio_pci_core_enable(vdev); + if (ret) + return ret; + + vfio_pci_core_finish_enable(vdev); + + mutex_init(&nvdev->memmap_lock); + + return 0; +} + +static void nvgrace_gpu_vfio_pci_close_device(struct vfio_device *core_vdev) +{ + struct nvgrace_gpu_vfio_pci_core_device *nvdev = container_of( + core_vdev, struct nvgrace_gpu_vfio_pci_core_device, core_device.vdev); + + if (nvdev->memmap) { + memunmap(nvdev->memmap); + nvdev->memmap = NULL; + } + + mutex_destroy(&nvdev->memmap_lock); + + vfio_pci_core_close_device(core_vdev); +} + +static int nvgrace_gpu_vfio_pci_mmap(struct vfio_device *core_vdev, + struct vm_area_struct *vma) +{ + struct nvgrace_gpu_vfio_pci_core_device *nvdev = container_of( + core_vdev, struct nvgrace_gpu_vfio_pci_core_device, core_device.vdev); + + unsigned long start_pfn; + unsigned int index; + u64 req_len, pgoff, end; + int ret = 0; + + index = vma->vm_pgoff >> (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT); + if (index != VFIO_PCI_BAR2_REGION_INDEX) + return vfio_pci_core_mmap(core_vdev, vma); + + /* + * Request to mmap the BAR. Map to the CPU accessible memory on the + * GPU using the memory information gathered from the system ACPI + * tables. + */ + pgoff = vma->vm_pgoff & + ((1U << (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT)) - 1); + + if (check_sub_overflow(vma->vm_end, vma->vm_start, &req_len) || + check_add_overflow(PHYS_PFN(nvdev->memphys), pgoff, &start_pfn) || + check_add_overflow(PFN_PHYS(pgoff), req_len, &end)) + return -EOVERFLOW; + + /* + * Check that the mapping request does not go beyond available device + * memory size + */ + if (end > nvdev->memlength) + return -EINVAL; + + /* + * Perform a PFN map to the memory and back the device BAR by the + * GPU memory. + * + * The available GPU memory size may not be power-of-2 aligned. Given + * that the memory is exposed as a BAR, the mapping request is of the + * power-of-2 aligned size. Map only up to the size of the GPU memory. + * If the memory access is beyond the actual GPU memory size, it will + * be handled by the vfio_device_ops read/write. + * + * During device reset, the GPU is safely disconnected to the CPU + * and access to the BAR will be immediately returned preventing + * machine check. + */ + ret = remap_pfn_range(vma, vma->vm_start, start_pfn, + req_len, vma->vm_page_prot); + if (ret) + return ret; + + vma->vm_pgoff = start_pfn; + + return 0; +} + +static long +nvgrace_gpu_vfio_pci_ioctl_get_region_info(struct vfio_device *core_vdev, + unsigned long arg) +{ + unsigned long minsz = offsetofend(struct vfio_region_info, offset); + struct nvgrace_gpu_vfio_pci_core_device *nvdev = container_of( + core_vdev, struct nvgrace_gpu_vfio_pci_core_device, core_device.vdev); + struct vfio_region_info info; + + if (copy_from_user(&info, (void __user *)arg, minsz)) + return -EFAULT; + + if (info.argsz < minsz) + return -EINVAL; + + if (info.index == VFIO_PCI_BAR2_REGION_INDEX) { + /* + * Request to determine the BAR region information. Send the + * GPU memory information. + */ + uint32_t size; + int ret; + struct vfio_region_info_cap_sparse_mmap *sparse; + struct vfio_info_cap caps = { .buf = NULL, .size = 0 }; + + size = struct_size(sparse, areas, 1); + + /* + * Setup for sparse mapping for the device memory. Only the + * available device memory on the hardware is shown as a + * mappable region. + */ + sparse = kzalloc(size, GFP_KERNEL); + if (!sparse) + return -ENOMEM; + + sparse->nr_areas = 1; + sparse->areas[0].offset = 0; + sparse->areas[0].size = nvdev->memlength; + sparse->header.id = VFIO_REGION_INFO_CAP_SPARSE_MMAP; + sparse->header.version = 1; + + ret = vfio_info_add_capability(&caps, &sparse->header, size); + kfree(sparse); + if (ret) + return ret; + + info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); + /* + * The available GPU memory size may not be power-of-2 aligned. + * Given that the memory is exposed as a BAR and may not be + * aligned, roundup to the next power-of-2. + */ + info.size = roundup_pow_of_two(nvdev->memlength); + info.flags = VFIO_REGION_INFO_FLAG_READ | + VFIO_REGION_INFO_FLAG_WRITE | + VFIO_REGION_INFO_FLAG_MMAP; + + if (caps.size) { + info.flags |= VFIO_REGION_INFO_FLAG_CAPS; + if (info.argsz < sizeof(info) + caps.size) { + info.argsz = sizeof(info) + caps.size; + info.cap_offset = 0; + } else { + vfio_info_cap_shift(&caps, sizeof(info)); + if (copy_to_user((void __user *)arg + + sizeof(info), caps.buf, + caps.size)) { + kfree(caps.buf); + return -EFAULT; + } + info.cap_offset = sizeof(info); + } + kfree(caps.buf); + } + return copy_to_user((void __user *)arg, &info, minsz) ? + -EFAULT : 0; + } + return vfio_pci_core_ioctl(core_vdev, VFIO_DEVICE_GET_REGION_INFO, arg); +} + +static long nvgrace_gpu_vfio_pci_ioctl(struct vfio_device *core_vdev, + unsigned int cmd, unsigned long arg) +{ + if (cmd == VFIO_DEVICE_GET_REGION_INFO) + return nvgrace_gpu_vfio_pci_ioctl_get_region_info(core_vdev, arg); + + return vfio_pci_core_ioctl(core_vdev, cmd, arg); +} + +/* + * Read count bytes from the device memory at an offset. The actual device + * memory size (available) may not be a power-of-2. So the driver fakes + * the size to a power-of-2 (reported) when exposing to a user space driver. + * + * Read request beyond the actual device size is filled with ~0, while + * those beyond the actual reported size is skipped. + * + * A read from a negative or a reported+ offset, a negative count are + * considered error conditions and returned with an -EINVAL. + */ +ssize_t nvgrace_gpu_read_mem(void __user *buf, size_t count, loff_t *ppos, + struct nvgrace_gpu_vfio_pci_core_device *nvdev) +{ + u64 offset = *ppos & VFIO_PCI_OFFSET_MASK; + size_t mem_count, i, bar_size = roundup_pow_of_two(nvdev->memlength); + u8 val = 0xFF; + + if (offset >= bar_size) + return -EINVAL; + + /* Clip short the read request beyond reported BAR size */ + count = min(count, bar_size - (size_t)offset); + + /* + * Determine how many bytes to be actually read from the device memory. + * Do not read from the offset beyond available size. + */ + if (offset >= nvdev->memlength) + mem_count = 0; + else + mem_count = min(count, nvdev->memlength - (size_t)offset); + + /* + * Handle read on the BAR2 region. Map to the target device memory + * physical address and copy to the request read buffer. + */ + if (copy_to_user(buf, (u8 *)nvdev->memmap + offset, mem_count)) + return -EFAULT; + + /* + * Only the device memory present on the hardware is mapped, which may + * not be power-of-2 aligned. A read to the BAR2 region implies an + * access outside the available device memory on the hardware. Fill + * such read request with ~0. + */ + for (i = mem_count; i < count; i++) + put_user(val, (unsigned char __user *)(buf + i)); + + return count; +} + +static ssize_t nvgrace_gpu_vfio_pci_read(struct vfio_device *core_vdev, + char __user *buf, size_t count, loff_t *ppos) +{ + unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); + struct nvgrace_gpu_vfio_pci_core_device *nvdev = container_of( + core_vdev, struct nvgrace_gpu_vfio_pci_core_device, core_device.vdev); + + if (index == VFIO_PCI_BAR2_REGION_INDEX) { + mutex_lock(&nvdev->memmap_lock); + if (!nvdev->memmap) { + nvdev->memmap = memremap(nvdev->memphys, nvdev->memlength, MEMREMAP_WB); + if (!nvdev->memmap) { + mutex_unlock(&nvdev->memmap_lock); + return -ENOMEM; + } + } + mutex_unlock(&nvdev->memmap_lock); + + return nvgrace_gpu_read_mem(buf, count, ppos, nvdev); + } + + return vfio_pci_core_read(core_vdev, buf, count, ppos); +} + +/* + * Write count bytes to the device memory at a given offset. The actual device + * memory size (available) may not be a power-of-2. So the driver fakes the + * size to a power-of-2 (reported) when exposing to a user space driver. + * + * Write request beyond the actual device size are dropped, while those + * beyond the actual reported size are skipped entirely. + * + * A write to a negative or a reported+ offset, a negative count are + * considered error conditions and returned with an -EINVAL. + */ +ssize_t nvgrace_gpu_write_mem(size_t count, loff_t *ppos, const void __user *buf, + struct nvgrace_gpu_vfio_pci_core_device *nvdev) +{ + u64 offset = *ppos & VFIO_PCI_OFFSET_MASK; + size_t mem_count, bar_size = roundup_pow_of_two(nvdev->memlength); + + if (offset >= bar_size) + return -EINVAL; + + /* Clip short the read request beyond reported BAR size */ + count = min(count, bar_size - (size_t)offset); + + /* + * Determine how many bytes to be actually written to the device memory. + * Do not write to the offset beyond available size. + */ + if (offset >= nvdev->memlength) + mem_count = 0; + else + mem_count = min(count, nvdev->memlength - (size_t)offset); + + /* + * Only the device memory present on the hardware is mapped, which may + * not be power-of-2 aligned. A write to the BAR2 region implies an + * access outside the available device memory on the hardware. Drop + * those write requests. + */ + if (copy_from_user((u8 *)nvdev->memmap + offset, buf, mem_count)) + return -EFAULT; + + return count; +} + +static ssize_t nvgrace_gpu_vfio_pci_write(struct vfio_device *core_vdev, + const char __user *buf, size_t count, loff_t *ppos) +{ + unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); + struct nvgrace_gpu_vfio_pci_core_device *nvdev = container_of( + core_vdev, struct nvgrace_gpu_vfio_pci_core_device, core_device.vdev); + + if (index == VFIO_PCI_BAR2_REGION_INDEX) { + mutex_lock(&nvdev->memmap_lock); + if (!nvdev->memmap) { + nvdev->memmap = memremap(nvdev->memphys, nvdev->memlength, MEMREMAP_WB); + if (!nvdev->memmap) { + mutex_unlock(&nvdev->memmap_lock); + return -ENOMEM; + } + } + mutex_unlock(&nvdev->memmap_lock); + + return nvgrace_gpu_write_mem(count, ppos, buf, nvdev); + } + + return vfio_pci_core_write(core_vdev, buf, count, ppos); +} + +static const struct vfio_device_ops nvgrace_gpu_vfio_pci_ops = { + .name = "nvgrace-gpu-vfio-pci", + .init = vfio_pci_core_init_dev, + .release = vfio_pci_core_release_dev, + .open_device = nvgrace_gpu_vfio_pci_open_device, + .close_device = nvgrace_gpu_vfio_pci_close_device, + .ioctl = nvgrace_gpu_vfio_pci_ioctl, + .read = nvgrace_gpu_vfio_pci_read, + .write = nvgrace_gpu_vfio_pci_write, + .mmap = nvgrace_gpu_vfio_pci_mmap, + .request = vfio_pci_core_request, + .match = vfio_pci_core_match, + .bind_iommufd = vfio_iommufd_physical_bind, + .unbind_iommufd = vfio_iommufd_physical_unbind, + .attach_ioas = vfio_iommufd_physical_attach_ioas, +}; + +static struct +nvgrace_gpu_vfio_pci_core_device *nvgrace_gpu_drvdata(struct pci_dev *pdev) +{ + struct vfio_pci_core_device *core_device = dev_get_drvdata(&pdev->dev); + + return container_of(core_device, struct nvgrace_gpu_vfio_pci_core_device, + core_device); +} + +static int +nvgrace_gpu_vfio_pci_fetch_memory_property(struct pci_dev *pdev, + struct nvgrace_gpu_vfio_pci_core_device *nvdev) +{ + int ret; + u64 memphys, memlength; + + /* + * The memory information is present in the system ACPI tables as DSD + * properties nvidia,gpu-mem-base-pa and nvidia,gpu-mem-size. + */ + ret = device_property_read_u64(&pdev->dev, "nvidia,gpu-mem-base-pa", + &(memphys)); + if (ret) + goto done; + + if (memphys > type_max(phys_addr_t)) { + ret = -EOVERFLOW; + goto done; + } + + nvdev->memphys = memphys; + + ret = device_property_read_u64(&pdev->dev, "nvidia,gpu-mem-size", + &(memlength)); + if (ret) + goto done; + + if (memlength > type_max(size_t)) { + ret = -EOVERFLOW; + goto done; + } + + /* + * If the C2C link is not up due to an error, the coherent device + * memory size is returned as 0. Fail in such case. + */ + if (memlength == 0) { + ret = -ENOMEM; + goto done; + } + + nvdev->memlength = memlength; + +done: + return ret; +} + +static int nvgrace_gpu_vfio_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + struct nvgrace_gpu_vfio_pci_core_device *nvdev; + int ret; + + nvdev = vfio_alloc_device(nvgrace_gpu_vfio_pci_core_device, core_device.vdev, + &pdev->dev, &nvgrace_gpu_vfio_pci_ops); + if (IS_ERR(nvdev)) + return PTR_ERR(nvdev); + + dev_set_drvdata(&pdev->dev, nvdev); + + ret = nvgrace_gpu_vfio_pci_fetch_memory_property(pdev, nvdev); + if (ret) + goto out_put_vdev; + + ret = vfio_pci_core_register_device(&nvdev->core_device); + if (ret) + goto out_put_vdev; + + return ret; + +out_put_vdev: + vfio_put_device(&nvdev->core_device.vdev); + return ret; +} + +static void nvgrace_gpu_vfio_pci_remove(struct pci_dev *pdev) +{ + struct nvgrace_gpu_vfio_pci_core_device *nvdev = nvgrace_gpu_drvdata(pdev); + struct vfio_pci_core_device *vdev = &nvdev->core_device; + + vfio_pci_core_unregister_device(vdev); + vfio_put_device(&vdev->vdev); +} + +static const struct pci_device_id nvgrace_gpu_vfio_pci_table[] = { + /* GH200 120GB */ + { PCI_DRIVER_OVERRIDE_DEVICE_VFIO(PCI_VENDOR_ID_NVIDIA, 0x2342) }, + /* GH200 480GB */ + { PCI_DRIVER_OVERRIDE_DEVICE_VFIO(PCI_VENDOR_ID_NVIDIA, 0x2345) }, + {} +}; + +MODULE_DEVICE_TABLE(pci, nvgrace_gpu_vfio_pci_table); + +static struct pci_driver nvgrace_gpu_vfio_pci_driver = { + .name = KBUILD_MODNAME, + .id_table = nvgrace_gpu_vfio_pci_table, + .probe = nvgrace_gpu_vfio_pci_probe, + .remove = nvgrace_gpu_vfio_pci_remove, + .err_handler = &vfio_pci_core_err_handlers, + .driver_managed_dma = true, +}; + +module_pci_driver(nvgrace_gpu_vfio_pci_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Ankit Agrawal <ankita@nvidia.com>"); +MODULE_AUTHOR("Aniket Agashe <aniketa@nvidia.com>"); +MODULE_DESCRIPTION( + "VFIO NVGRACE GPU PF - User Level driver for NVIDIA devices with CPU coherently accessible device memory");