| Message ID | 20230912073521.2106162-1-andrzej.hajda@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/gt: skip WA verfication for GEN7_MISCCPCTL on DG2 | expand |
On 12.09.2023 09:35, Andrzej Hajda wrote: > Some DG2 firmware locks this register for modification. Using wa_add > with read_mask 0 allows to skip checks of such registers. > > Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> Forgot to add tag: Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8945 Regards Andrzej > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 70071ead0659cc..1d1474ad945e0c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1597,8 +1597,11 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) > /* Wa_14014830051:dg2 */ > wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); > > - /* Wa_14015795083 */ > - wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); > + /* Wa_14015795083 > + * Skip verification for possibly locked register. > + */ > + wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE, > + 0, 0, false); > > /* Wa_18018781329 */ > wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
On 9/12/2023 9:35 AM, Andrzej Hajda wrote: > Some DG2 firmware locks this register for modification. Using wa_add > with read_mask 0 allows to skip checks of such registers. > > Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 70071ead0659cc..1d1474ad945e0c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1597,8 +1597,11 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) > /* Wa_14014830051:dg2 */ > wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); > > - /* Wa_14015795083 */ > - wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); > + /* Wa_14015795083 > + * Skip verification for possibly locked register. > + */ > + wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE, > + 0, 0, false); > > /* Wa_18018781329 */ > wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
On Tue, Sep 12, 2023 at 09:35:21AM +0200, Andrzej Hajda wrote: > Some DG2 firmware locks this register for modification. Using wa_add > with read_mask 0 allows to skip checks of such registers. > > Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 70071ead0659cc..1d1474ad945e0c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1597,8 +1597,11 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) > /* Wa_14014830051:dg2 */ > wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); > > - /* Wa_14015795083 */ > - wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); > + /* Wa_14015795083 Minor nitpick: kernel coding style says that "/*" should be on a line by itself for multi-line comments. Aside from that, Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Matt > + * Skip verification for possibly locked register. > + */ > + wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE, > + 0, 0, false); > > /* Wa_18018781329 */ > wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); > -- > 2.34.1 >
On 12.09.2023 23:05, Matt Roper wrote: > On Tue, Sep 12, 2023 at 09:35:21AM +0200, Andrzej Hajda wrote: >> Some DG2 firmware locks this register for modification. Using wa_add >> with read_mask 0 allows to skip checks of such registers. >> >> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> >> --- >> drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++-- >> 1 file changed, 5 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> index 70071ead0659cc..1d1474ad945e0c 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c >> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> @@ -1597,8 +1597,11 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) >> /* Wa_14014830051:dg2 */ >> wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); >> >> - /* Wa_14015795083 */ >> - wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); >> + /* Wa_14015795083 > > Minor nitpick: kernel coding style says that "/*" should be on a line > by itself for multi-line comments. Aside from that, > > Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Thanks for both r-b. Pushed with adjusted comment. Regards Andrzej > > > Matt > >> + * Skip verification for possibly locked register. >> + */ >> + wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE, >> + 0, 0, false); >> >> /* Wa_18018781329 */ >> wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); >> -- >> 2.34.1 >> >
Hi Andrzej, On Tue, Sep 12, 2023 at 09:35:21AM +0200, Andrzej Hajda wrote: > Some DG2 firmware locks this register for modification. Using wa_add > with read_mask 0 allows to skip checks of such registers. > > Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Andi > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 70071ead0659cc..1d1474ad945e0c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1597,8 +1597,11 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) > /* Wa_14014830051:dg2 */ > wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); > > - /* Wa_14015795083 */ > - wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); > + /* Wa_14015795083 > + * Skip verification for possibly locked register. > + */ > + wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE, > + 0, 0, false); > > /* Wa_18018781329 */ > wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); > -- > 2.34.1
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 70071ead0659cc..1d1474ad945e0c 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1597,8 +1597,11 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) /* Wa_14014830051:dg2 */ wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); - /* Wa_14015795083 */ - wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); + /* Wa_14015795083 + * Skip verification for possibly locked register. + */ + wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE, + 0, 0, false); /* Wa_18018781329 */ wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
Some DG2 firmware locks this register for modification. Using wa_add with read_mask 0 allows to skip checks of such registers. Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)