| Message ID | 20230904115517.458662-3-vinod.govindapillai@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | fbc on any planes | expand |
On Mon, Sep 04, 2023 at 02:55:17PM +0300, Vinod Govindapillai wrote: > For LNL onwards, FBC can be supported on planes with per > pixel alpha > > Bspec: 69560 > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> > --- > drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > index a3999ad95a19..c0e4caec03ea 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -1209,7 +1209,8 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, > return 0; > } > > - if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && > + if (DISPLAY_VER(i915) < 20 && Bspec still says 15. Someone needs to figure this mess out for all LNL patches. > + plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && > fb->format->has_alpha) { We would have already rejected the pixel format earlier, so atm this check is redundant. > plane_state->no_fbc_reason = "per-pixel alpha not supported"; > return 0; > -- > 2.34.1
Hi Ville, It was confirmed by Jani Nikula that it is 20. Here is his comments. ".... display ver 20 is what the hardware reports to us. the current info is at bspecb70821 if you scroll down to "LNL GMD Architecture IDs" " Br Vinod
On Wed, 2023-09-13 at 13:38 +0300, Ville Syrjälä wrote: > On Mon, Sep 04, 2023 at 02:55:17PM +0300, Vinod Govindapillai wrote: > > For LNL onwards, FBC can be supported on planes with per > > pixel alpha > > > > Bspec: 69560 > > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > > index a3999ad95a19..c0e4caec03ea 100644 > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > > @@ -1209,7 +1209,8 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, > > return 0; > > } > > > > - if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && > > + if (DISPLAY_VER(i915) < 20 && > > Bspec still says 15. Someone needs to figure this mess out for > all LNL patches. > > > + plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && > > fb->format->has_alpha) { > > We would have already rejected the pixel format earlier, so atm this > check is redundant. Hi, Could you please clarify this. This is an existing check and I just added to limit this versions before 20. As we have this FBC possibility to plane 0/1/2, isn't this restriction not applied to any of those planes as well. Though at the moment there is no possibility to set FBC any one of this possibility explicitly, we plan to have some IGT cases where we would like to validate this feature by having cases with only 0 or 1 or 2 plane and check FBC is enablement is okay. BR Vinod > > > plane_state->no_fbc_reason = "per-pixel alpha not supported"; > > return 0; > > -- > > 2.34.1 >
On Thu, Sep 21, 2023 at 08:34:35AM +0000, Govindapillai, Vinod wrote: > On Wed, 2023-09-13 at 13:38 +0300, Ville Syrjälä wrote: > > On Mon, Sep 04, 2023 at 02:55:17PM +0300, Vinod Govindapillai wrote: > > > For LNL onwards, FBC can be supported on planes with per > > > pixel alpha > > > > > > Bspec: 69560 > > > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++- > > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > > > index a3999ad95a19..c0e4caec03ea 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > > > @@ -1209,7 +1209,8 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, > > > return 0; > > > } > > > > > > - if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && > > > + if (DISPLAY_VER(i915) < 20 && > > > > Bspec still says 15. Someone needs to figure this mess out for > > all LNL patches. > > > > > + plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && > > > fb->format->has_alpha) { > > > > We would have already rejected the pixel format earlier, so atm this > > check is redundant. > > Hi, > > Could you please clarify this. pixel_format_is_valid()
On Wed, Sep 13, 2023 at 01:38:23PM +0300, Ville Syrjälä wrote: >On Mon, Sep 04, 2023 at 02:55:17PM +0300, Vinod Govindapillai wrote: >> For LNL onwards, FBC can be supported on planes with per >> pixel alpha >> >> Bspec: 69560 >> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> >> --- >> drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c >> index a3999ad95a19..c0e4caec03ea 100644 >> --- a/drivers/gpu/drm/i915/display/intel_fbc.c >> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c >> @@ -1209,7 +1209,8 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, >> return 0; >> } >> >> - if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && >> + if (DISPLAY_VER(i915) < 20 && > >Bspec still says 15. Someone needs to figure this mess out for >all LNL patches. The HW reports IP version 20. The name of the IP is "Xe2-LPD (formerly Display_15)". For checking the display version, we don't care about the name or former name, we care about what is in the GMD_ID. Lucas De Marchi > >> + plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && >> fb->format->has_alpha) { > >We would have already rejected the pixel format earlier, so atm this >check is redundant. > >> plane_state->no_fbc_reason = "per-pixel alpha not supported"; >> return 0; >> -- >> 2.34.1 > >-- >Ville Syrjälä >Intel
On Thu, Sep 21, 2023 at 08:22:23AM -0500, Lucas De Marchi wrote: > On Wed, Sep 13, 2023 at 01:38:23PM +0300, Ville Syrjälä wrote: > >On Mon, Sep 04, 2023 at 02:55:17PM +0300, Vinod Govindapillai wrote: > >> For LNL onwards, FBC can be supported on planes with per > >> pixel alpha > >> > >> Bspec: 69560 > >> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> > >> --- > >> drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++- > >> 1 file changed, 2 insertions(+), 1 deletion(-) > >> > >> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > >> index a3999ad95a19..c0e4caec03ea 100644 > >> --- a/drivers/gpu/drm/i915/display/intel_fbc.c > >> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > >> @@ -1209,7 +1209,8 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, > >> return 0; > >> } > >> > >> - if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && > >> + if (DISPLAY_VER(i915) < 20 && > > > >Bspec still says 15. Someone needs to figure this mess out for > >all LNL patches. > > The HW reports IP version 20. The name of the IP is "Xe2-LPD (formerly Display_15)". > For checking the display version, we don't care about the name or former > name, we care about what is in the GMD_ID. Well, we care what it actually means. If the bspec and hardware reported IP version all messed up how is one supposed to know what hardware has what features?
On Thu, Sep 21, 2023 at 08:23:52PM +0300, Ville Syrjälä wrote: >On Thu, Sep 21, 2023 at 08:22:23AM -0500, Lucas De Marchi wrote: >> On Wed, Sep 13, 2023 at 01:38:23PM +0300, Ville Syrjälä wrote: >> >On Mon, Sep 04, 2023 at 02:55:17PM +0300, Vinod Govindapillai wrote: >> >> For LNL onwards, FBC can be supported on planes with per >> >> pixel alpha >> >> >> >> Bspec: 69560 >> >> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> >> >> --- >> >> drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++- >> >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> >> >> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c >> >> index a3999ad95a19..c0e4caec03ea 100644 >> >> --- a/drivers/gpu/drm/i915/display/intel_fbc.c >> >> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c >> >> @@ -1209,7 +1209,8 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, >> >> return 0; >> >> } >> >> >> >> - if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && >> >> + if (DISPLAY_VER(i915) < 20 && >> > >> >Bspec still says 15. Someone needs to figure this mess out for >> >all LNL patches. >> >> The HW reports IP version 20. The name of the IP is "Xe2-LPD (formerly Display_15)". >> For checking the display version, we don't care about the name or former >> name, we care about what is in the GMD_ID. > >Well, we care what it actually means. If the bspec and hardware reported >IP version all messed up how is one supposed to know what hardware has what >features? Bspec says LNL has Display IP version 20. IP is called Xe2-LPD. Version is 20. In some places in the spec there are mentions to the old name. Someone probably needs to do a search and replace, but that is beyond what I can do. The version was never 15, that was part of the name. If you want to add a new source of confusion, in some places version is (was? can't find them anymore) marked in bspec as 0x14 so we had some early patches checking version 14 rather than 20 by mistake. None of the patches being upstreamed should have them anymore though. Lucas De Marchi > >-- >Ville Syrjälä >Intel
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index a3999ad95a19..c0e4caec03ea 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1209,7 +1209,8 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, return 0; } - if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && + if (DISPLAY_VER(i915) < 20 && + plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && fb->format->has_alpha) { plane_state->no_fbc_reason = "per-pixel alpha not supported"; return 0;
For LNL onwards, FBC can be supported on planes with per pixel alpha Bspec: 69560 Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> --- drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)