[10/37] clk: renesas: rzg2l: use core->name for clock name

Message ID	20230912045157.177966-11-claudiu.beznea.uj@bp.renesas.com (mailing list archive)
State	Superseded
Delegated to:	Geert Uytterhoeven
Headers	show Return-Path: <linux-renesas-soc-owner@vger.kernel.org> From: Claudiu <claudiu.beznea@tuxon.dev> To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, ulf.hansson@linaro.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com, quic_bjorande@quicinc.com, arnd@arndb.de, konrad.dybcio@linaro.org, neil.armstrong@linaro.org, nfraprado@collabora.com, rafal@milecki.pl, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Subject: [PATCH 10/37] clk: renesas: rzg2l: use core->name for clock name Date: Tue, 12 Sep 2023 07:51:30 +0300 Message-Id: <20230912045157.177966-11-claudiu.beznea.uj@bp.renesas.com> In-Reply-To: <20230912045157.177966-1-claudiu.beznea.uj@bp.renesas.com> References: <20230912045157.177966-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Add new Renesas RZ/G3S SoC and RZ/G3S SMARC EVK \| expand [00/37] Add new Renesas RZ/G3S SoC and RZ/G3S SMARC EVK [01/37] dt-bindings: serial: renesas,scif: document r9a08g045 support [02/37] dt-bindings: soc: renesas: document Renesas RZ/G3S SoC variants [03/37] dt-bindings: soc: renesas: renesas,rzg2l-sysc: document RZ/G3S SoC [04/37] soc: renesas: identify RZ/G3S SoC [05/37] soc: renesas: remove blank lines [06/37] clk: renesas: rzg2l: wait for status bit of SD mux before continuing [07/37] clk: renesas: rzg2l: lock around writes to mux register [08/37] clk: renesas: rzg2l: trust value returned by hardware [09/37] clk: renesas: rzg2l: fix computation formula [10/37] clk: renesas: rzg2l: use core->name for clock name [11/37] clk: renesas: rzg2l: simplify a bit the logic in rzg2l_mod_clock_endisable() [12/37] clk: renesas: rzg2l: reduce the critical area [13/37] clk: renesas: rzg2l: use FIELD_GET() for PLL register fields [14/37] clk: renesas: rzg2l: use u32 for flag and mux_flags [15/37] clk: renesas: rzg2l: add support for RZ/G3S PLL [16/37] clk: renesas: rzg2l: add struct clk_hw_data [17/37] clk: renesas: rzg2l: remove CPG_SDHI_DSEL from generic header [18/37] clk: renesas: rzg2l: refactor sd mux driver [19/37] clk: renesas: rzg2l: add a divider clock for RZ/G3S [20/37] dt-bindings: clock: renesas,rzg2l-cpg: document RZ/G3S SoC [21/37] dt-bindings: clock: add r9a08g045 CPG clocks and resets definitions [22/37] clk: renesas: add minimal boot support for RZ/G3S SoC [23/37] pinctrl: renesas: rzg2l: index all registers based on port offset [24/37] pinctrl: renesas: rzg2l: adapt for different SD, PWPR register offsets [25/37] pinctrl: renesas: rzg2l: adapt function number for RZ/G3S [26/37] pinctrl: renesas: rzg2l: move ds and oi to SoC specific configuration [27/37] pinctrl: renesas: rzg2l: add support for different ds values on different groups [28/37] pinctrl: renesas: rzg2l: make struct rzg2l_pinctrl_data::dedicated_pins constant [29/37] dt-bindings: pinctrl: renesas: document RZ/G3S SoC [30/37] pinctrl: renesas: rzg2l: add support for RZ/G3S SoC [31/37] dt-bindings: mmc: renesas,sdhi: Document RZ/G3S support [32/37] arm64: dts: renesas: add initial DTSI for RZ/G3S SoC [33/37] arm64: dts: renesas: rzg3l-smarc-som: add initial support for RZ/G3S SMARC Carrier-II SoM [34/37] arm64: dts: renesas: rzg3s-smarc: add initial device tree for RZ SMARC Carrier-II board [35/37] dt-bindings: arm: renesas: document SMARC Carrier-II EVK [36/37] arm64: dts: renesas: r9a08g045s33-smarc: add initial device tree for RZ/G3S SMARC EVK board [37/37] arm64: defconfig: enable RZ/G3S (R9A08G045) SoC

Message ID

20230912045157.177966-11-claudiu.beznea.uj@bp.renesas.com (mailing list archive)

State

Superseded

Delegated to:

Geert Uytterhoeven

Headers

From: Claudiu <claudiu.beznea@tuxon.dev>
To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org,
        robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        conor+dt@kernel.org, ulf.hansson@linaro.org,
        linus.walleij@linaro.org, gregkh@linuxfoundation.org,
        jirislaby@kernel.org, magnus.damm@gmail.com,
        catalin.marinas@arm.com, will@kernel.org,
        prabhakar.mahadev-lad.rj@bp.renesas.com,
        biju.das.jz@bp.renesas.com, quic_bjorande@quicinc.com,
        arnd@arndb.de, konrad.dybcio@linaro.org, neil.armstrong@linaro.org,
        nfraprado@collabora.com, rafal@milecki.pl,
        wsa+renesas@sang-engineering.com
Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org,
        linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: [PATCH 10/37] clk: renesas: rzg2l: use core->name for clock name
Date: Tue, 12 Sep 2023 07:51:30 +0300
Message-Id: <20230912045157.177966-11-claudiu.beznea.uj@bp.renesas.com>
In-Reply-To: <20230912045157.177966-1-claudiu.beznea.uj@bp.renesas.com>
References: <20230912045157.177966-1-claudiu.beznea.uj@bp.renesas.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

Series

Add new Renesas RZ/G3S SoC and RZ/G3S SMARC EVK | expand

Commit Message

Claudiu Beznea Sept. 12, 2023, 4:51 a.m. UTC

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

core->name already contains the clock name thus, there is no
need to check the GET_SHIFT(core->conf) to decide on it.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 drivers/clk/renesas/rzg2l-cpg.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Geert Uytterhoeven Sept. 14, 2023, 1:04 p.m. UTC | #1

Hi Claudiu,

On Tue, Sep 12, 2023 at 6:52 AM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> core->name already contains the clock name thus, there is no
> need to check the GET_SHIFT(core->conf) to decide on it.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -266,7 +266,7 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core,
>         clk_hw_data->priv = priv;
>         clk_hw_data->conf = core->conf;
>
> -       init.name = GET_SHIFT(core->conf) ? "sd1" : "sd0";
> +       init.name = core->name;

Note that this does change the case of the names (e.g. "SD0" => "sd0").
I guess no one cares...

>         init.ops = &rzg2l_cpg_sd_clk_mux_ops;
>         init.flags = 0;
>         init.num_parents = core->num_parents;

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

Claudiu Beznea Sept. 15, 2023, 5:47 a.m. UTC | #2

On 14.09.2023 16:04, Geert Uytterhoeven wrote:
> Hi Claudiu,
> 
> On Tue, Sep 12, 2023 at 6:52 AM Claudiu <claudiu.beznea@tuxon.dev> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> core->name already contains the clock name thus, there is no
>> need to check the GET_SHIFT(core->conf) to decide on it.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> Thanks for your patch!
> 
>> --- a/drivers/clk/renesas/rzg2l-cpg.c
>> +++ b/drivers/clk/renesas/rzg2l-cpg.c
>> @@ -266,7 +266,7 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core,
>>         clk_hw_data->priv = priv;
>>         clk_hw_data->conf = core->conf;
>>
>> -       init.name = GET_SHIFT(core->conf) ? "sd1" : "sd0";
>> +       init.name = core->name;
> 
> Note that this does change the case of the names (e.g. "SD0" => "sd0").
> I guess no one cares...

As of my experiments and investigation we should be good with it.

> 
>>         init.ops = &rzg2l_cpg_sd_clk_mux_ops;
>>         init.flags = 0;
>>         init.num_parents = core->num_parents;
> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
>

Geert Uytterhoeven Sept. 18, 2023, 8:03 a.m. UTC | #3

On Fri, Sep 15, 2023 at 7:47 AM claudiu beznea <claudiu.beznea@tuxon.dev> wrote:
> On 14.09.2023 16:04, Geert Uytterhoeven wrote:
> > On Tue, Sep 12, 2023 at 6:52 AM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>
> >> core->name already contains the clock name thus, there is no
> >> need to check the GET_SHIFT(core->conf) to decide on it.
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> >> --- a/drivers/clk/renesas/rzg2l-cpg.c
> >> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> >> @@ -266,7 +266,7 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core,
> >>         clk_hw_data->priv = priv;
> >>         clk_hw_data->conf = core->conf;
> >>
> >> -       init.name = GET_SHIFT(core->conf) ? "sd1" : "sd0";
> >> +       init.name = core->name;
> >
> > Note that this does change the case of the names (e.g. "SD0" => "sd0").
> > I guess no one cares...
>
> As of my experiments and investigation we should be good with it.

Thx, will queue in renesas-clk-for-v6.7.

Gr{oetje,eeting}s,

                        Geert

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index b391c9548421..44226682db2c 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -266,7 +266,7 @@  rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core,
 	clk_hw_data->priv = priv;
 	clk_hw_data->conf = core->conf;
 
-	init.name = GET_SHIFT(core->conf) ? "sd1" : "sd0";
+	init.name = core->name;
 	init.ops = &rzg2l_cpg_sd_clk_mux_ops;
 	init.flags = 0;
 	init.num_parents = core->num_parents;

[10/37] clk: renesas: rzg2l: use core->name for clock name

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