| Message ID | 888d57a2d5e62affb8e29e0098402e428facd969.1695189879.git.wangchen20@iscas.ac.cn (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add Milk-V Pioneer RISC-V board support | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Series has a cover letter |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD 0bb80ecc33a8 |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 6 and now 6 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 9 this patch: 9 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 9 this patch: 9 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 29 this patch: 29 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 17 lines checked |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Wed, Sep 20, 2023 at 2:40 PM Chen Wang <unicornxw@gmail.com> wrote: > > From: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > Add quirk to skip setting the input clock rate for the uarts on the > Sophgo SG2042 SoC similar to the StarFive JH7100. > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn> > --- > drivers/tty/serial/8250/8250_dw.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c > index f4cafca1a7da..6c344877a07f 100644 > --- a/drivers/tty/serial/8250/8250_dw.c > +++ b/drivers/tty/serial/8250/8250_dw.c > @@ -770,7 +770,7 @@ static const struct dw8250_platform_data dw8250_renesas_rzn1_data = { > .quirks = DW_UART_QUIRK_IS_DMA_FC, > }; > > -static const struct dw8250_platform_data dw8250_starfive_jh7100_data = { > +static const struct dw8250_platform_data dw8250_skip_set_rate_data = { > .usr_reg = DW_UART_USR, > .quirks = DW_UART_QUIRK_SKIP_SET_RATE, > }; > @@ -780,7 +780,8 @@ static const struct of_device_id dw8250_of_match[] = { > { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data }, > { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data }, > { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data }, > - { .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data }, > + { .compatible = "sophgo,sg2042-uart", .data = &dw8250_skip_set_rate_data }, > + { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data }, Why shall we touch the jh7100 stuff in this patch? > { /* Sentinel */ } > }; > MODULE_DEVICE_TABLE(of, dw8250_of_match); > -- > 2.25.1 >
Ren, thanks for your review. sg2042 and jh7100 use the same uart driver and we here just want to reuse the logic from jh7100. We don't touch jh7100 stuff, we just rename "dw8250_starfive_jh7100_data" to "dw8250_skip_set_rate_data" and make it a common data for both sg2042 and jh7100. 在 2023/9/20 15:53, Guo Ren 写道: > On Wed, Sep 20, 2023 at 2:40 PM Chen Wang <unicornxw@gmail.com> wrote: >> From: Emil Renner Berthing <emil.renner.berthing@canonical.com> >> >> Add quirk to skip setting the input clock rate for the uarts on the >> Sophgo SG2042 SoC similar to the StarFive JH7100. >> >> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> >> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn> >> --- >> drivers/tty/serial/8250/8250_dw.c | 5 +++-- >> 1 file changed, 3 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c >> index f4cafca1a7da..6c344877a07f 100644 >> --- a/drivers/tty/serial/8250/8250_dw.c >> +++ b/drivers/tty/serial/8250/8250_dw.c >> @@ -770,7 +770,7 @@ static const struct dw8250_platform_data dw8250_renesas_rzn1_data = { >> .quirks = DW_UART_QUIRK_IS_DMA_FC, >> }; >> >> -static const struct dw8250_platform_data dw8250_starfive_jh7100_data = { >> +static const struct dw8250_platform_data dw8250_skip_set_rate_data = { >> .usr_reg = DW_UART_USR, >> .quirks = DW_UART_QUIRK_SKIP_SET_RATE, >> }; >> @@ -780,7 +780,8 @@ static const struct of_device_id dw8250_of_match[] = { >> { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data }, >> { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data }, >> { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data }, >> - { .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data }, >> + { .compatible = "sophgo,sg2042-uart", .data = &dw8250_skip_set_rate_data }, >> + { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data }, > Why shall we touch the jh7100 stuff in this patch? > >> { /* Sentinel */ } >> }; >> MODULE_DEVICE_TABLE(of, dw8250_of_match); >> -- >> 2.25.1 >> >
On Wed, Sep 20, 2023 at 4:06 PM Chen Wang <unicorn_wang@outlook.com> wrote: > > Ren, thanks for your review. > > sg2042 and jh7100 use the same uart driver and we here just want to reuse the logic from jh7100. > We don't touch jh7100 stuff, we just rename "dw8250_starfive_jh7100_data" to "dw8250_skip_set_rate_data" and make it a common data for both sg2042 and jh7100. Okay, I got it now. LGTM Reviewed-by: Guo Ren <guoren@kernel.org> > > 在 2023/9/20 15:53, Guo Ren 写道: > > On Wed, Sep 20, 2023 at 2:40 PM Chen Wang <unicornxw@gmail.com> wrote: > >> From: Emil Renner Berthing <emil.renner.berthing@canonical.com> > >> > >> Add quirk to skip setting the input clock rate for the uarts on the > >> Sophgo SG2042 SoC similar to the StarFive JH7100. > >> > >> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > >> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn> > >> --- > >> drivers/tty/serial/8250/8250_dw.c | 5 +++-- > >> 1 file changed, 3 insertions(+), 2 deletions(-) > >> > >> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c > >> index f4cafca1a7da..6c344877a07f 100644 > >> --- a/drivers/tty/serial/8250/8250_dw.c > >> +++ b/drivers/tty/serial/8250/8250_dw.c > >> @@ -770,7 +770,7 @@ static const struct dw8250_platform_data dw8250_renesas_rzn1_data = { > >> .quirks = DW_UART_QUIRK_IS_DMA_FC, > >> }; > >> > >> -static const struct dw8250_platform_data dw8250_starfive_jh7100_data = { > >> +static const struct dw8250_platform_data dw8250_skip_set_rate_data = { > >> .usr_reg = DW_UART_USR, > >> .quirks = DW_UART_QUIRK_SKIP_SET_RATE, > >> }; > >> @@ -780,7 +780,8 @@ static const struct of_device_id dw8250_of_match[] = { > >> { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data }, > >> { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data }, > >> { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data }, > >> - { .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data }, > >> + { .compatible = "sophgo,sg2042-uart", .data = &dw8250_skip_set_rate_data }, > >> + { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data }, > > Why shall we touch the jh7100 stuff in this patch? > > > >> { /* Sentinel */ } > >> }; > >> MODULE_DEVICE_TABLE(of, dw8250_of_match); > >> -- > >> 2.25.1 > >> > >
On 20/09/2023 07:40, Chen Wang wrote: > From: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > Add quirk to skip setting the input clock rate for the uarts on the > Sophgo SG2042 SoC similar to the StarFive JH7100. I'd love an actual explanation of why this is necessary here. > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn> > --- > drivers/tty/serial/8250/8250_dw.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c > index f4cafca1a7da..6c344877a07f 100644 > --- a/drivers/tty/serial/8250/8250_dw.c > +++ b/drivers/tty/serial/8250/8250_dw.c > @@ -770,7 +770,7 @@ static const struct dw8250_platform_data dw8250_renesas_rzn1_data = { > .quirks = DW_UART_QUIRK_IS_DMA_FC, > }; > > -static const struct dw8250_platform_data dw8250_starfive_jh7100_data = { > +static const struct dw8250_platform_data dw8250_skip_set_rate_data = { > .usr_reg = DW_UART_USR, > .quirks = DW_UART_QUIRK_SKIP_SET_RATE, > }; > @@ -780,7 +780,8 @@ static const struct of_device_id dw8250_of_match[] = { > { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data }, > { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data }, > { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data }, > - { .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data }, > + { .compatible = "sophgo,sg2042-uart", .data = &dw8250_skip_set_rate_data }, > + { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data }, > { /* Sentinel */ } > }; > MODULE_DEVICE_TABLE(of, dw8250_of_match);
Ben Dooks wrote: > On 20/09/2023 07:40, Chen Wang wrote: > > From: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > > > Add quirk to skip setting the input clock rate for the uarts on the > > Sophgo SG2042 SoC similar to the StarFive JH7100. > > I'd love an actual explanation of why this is necessary here. Makes sense. For the JH7100 the commit message is: On the StarFive JH7100 RISC-V SoC the UART core clocks can't be set to exactly 16 * 115200Hz and many other common bitrates. Trying this will only result in a higher input clock, but low enough that the UART's internal divisor can't come close enough to the baud rate target. So rather than try to set the input clock it's better to skip the clk_set_rate call and rely solely on the UART's internal divisor. @Chen Wang is this also true for the SG2042? /Emil
Regards, unicornx Emil Renner Berthing <emil.renner.berthing@canonical.com> 于2023年9月22日周五 18:40写道： > > Ben Dooks wrote: > > On 20/09/2023 07:40, Chen Wang wrote: > > > From: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > > > > > Add quirk to skip setting the input clock rate for the uarts on the > > > Sophgo SG2042 SoC similar to the StarFive JH7100. > > > > I'd love an actual explanation of why this is necessary here. > > Makes sense. For the JH7100 the commit message is: > > On the StarFive JH7100 RISC-V SoC the UART core clocks can't be set to > exactly 16 * 115200Hz and many other common bitrates. Trying this will > only result in a higher input clock, but low enough that the UART's > internal divisor can't come close enough to the baud rate target. > So rather than try to set the input clock it's better to skip the > clk_set_rate call and rely solely on the UART's internal divisor. > > @Chen Wang is this also true for the SG2042? > > /Emil Emil & Ben, I need to double-confirm this with sophgo engineers. Because they are off work now, I will probably get back to you later next week.
Emil Renner Berthing <emil.renner.berthing@canonical.com> 于2023年9月22日周五 18:40写道： > > Ben Dooks wrote: > > On 20/09/2023 07:40, Chen Wang wrote: > > > From: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > > > > > Add quirk to skip setting the input clock rate for the uarts on the > > > Sophgo SG2042 SoC similar to the StarFive JH7100. > > > > I'd love an actual explanation of why this is necessary here. > > Makes sense. For the JH7100 the commit message is: > > On the StarFive JH7100 RISC-V SoC the UART core clocks can't be set to > exactly 16 * 115200Hz and many other common bitrates. Trying this will > only result in a higher input clock, but low enough that the UART's > internal divisor can't come close enough to the baud rate target. > So rather than try to set the input clock it's better to skip the > clk_set_rate call and rely solely on the UART's internal divisor. > > @Chen Wang is this also true for the SG2042? > > /Emil Emil & Ben, After double-checking with Sophgo engineers and doing more investigation, we think the original changes(quirk to skip setting the input clock) on UART may not be required. Due to currently, the target of this patchset is just to enable a minimal system and no clock relateding changes are included yet. I will first remove this quirk change on UART and use the fixed frequence - 500M - and reply solely on the UART's internal divisor to work. We will re-evaluate this quirk change in next patchset when we involve clock related stuff. Looping Haijiao, engineer from Sophgo, who is working on clock on sg2042. Regards, Chen
diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index f4cafca1a7da..6c344877a07f 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -770,7 +770,7 @@ static const struct dw8250_platform_data dw8250_renesas_rzn1_data = { .quirks = DW_UART_QUIRK_IS_DMA_FC, }; -static const struct dw8250_platform_data dw8250_starfive_jh7100_data = { +static const struct dw8250_platform_data dw8250_skip_set_rate_data = { .usr_reg = DW_UART_USR, .quirks = DW_UART_QUIRK_SKIP_SET_RATE, }; @@ -780,7 +780,8 @@ static const struct of_device_id dw8250_of_match[] = { { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data }, { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data }, { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data }, - { .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data }, + { .compatible = "sophgo,sg2042-uart", .data = &dw8250_skip_set_rate_data }, + { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, dw8250_of_match);