diff mbox series

[v2] riscv: dts: thead: set dma-noncoherent to soc bus

Message ID 20230912072232.2455-1-jszhang@kernel.org (mailing list archive)
State Accepted
Commit 759426c758c7053a941a4c06c7571461439fcff6
Delegated to: Conor Dooley
Headers show
Series [v2] riscv: dts: thead: set dma-noncoherent to soc bus | expand

Checks

Context Check Description
conchuod/patch-1-test-13 success .github/scripts/patches/verify_signedoff.sh
conchuod/vmtest-for-next-PR success PR summary
conchuod/patch-1-test-1 success .github/scripts/patches/build_rv32_defconfig.sh
conchuod/patch-1-test-2 success .github/scripts/patches/build_rv64_clang_allmodconfig.sh
conchuod/patch-1-test-3 success .github/scripts/patches/build_rv64_gcc_allmodconfig.sh
conchuod/patch-1-test-4 success .github/scripts/patches/build_rv64_nommu_k210_defconfig.sh
conchuod/patch-1-test-5 success .github/scripts/patches/build_rv64_nommu_virt_defconfig.sh
conchuod/patch-1-test-6 success .github/scripts/patches/checkpatch.sh
conchuod/patch-1-test-7 success .github/scripts/patches/dtb_warn_rv64.sh
conchuod/patch-1-test-8 success .github/scripts/patches/header_inline.sh
conchuod/patch-1-test-9 success .github/scripts/patches/kdoc.sh
conchuod/patch-1-test-10 success .github/scripts/patches/module_param.sh
conchuod/patch-1-test-11 success .github/scripts/patches/verify_fixes.sh
conchuod/patch-1-test-12 success .github/scripts/patches/verify_signedoff.sh

Commit Message

Jisheng Zhang Sept. 12, 2023, 7:22 a.m. UTC 
riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
dma coherent, so set dma-noncoherent to reflect this fact.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Tested-by: Drew Fustini <dfustini@baylibre.com>
---

Since v1:
 - rebase on v6.6-rc1
 - collect Tested-by tag

 arch/riscv/boot/dts/thead/th1520.dtsi | 1 +
 1 file changed, 1 insertion(+)

Comments

Guo Ren Sept. 12, 2023, 2:48 p.m. UTC | #1 
On Tue, Sep 12, 2023 at 3:34 PM Jisheng Zhang <jszhang@kernel.org> wrote:
>
> riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
> dma coherent, so set dma-noncoherent to reflect this fact.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> Tested-by: Drew Fustini <dfustini@baylibre.com>
> ---
>
> Since v1:
>  - rebase on v6.6-rc1
>  - collect Tested-by tag
>
>  arch/riscv/boot/dts/thead/th1520.dtsi | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index ce708183b6f6..ff364709a6df 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -139,6 +139,7 @@ soc {
>                 interrupt-parent = <&plic>;
>                 #address-cells = <2>;
>                 #size-cells = <2>;
> +               dma-noncoherent;
Reviewed-by: Guo Ren <guoren@kernel.org>

>                 ranges;
>
>                 plic: interrupt-controller@ffd8000000 {
> --
> 2.40.1
>
Conor Dooley Sept. 12, 2023, 4:27 p.m. UTC | #2 
On Tue, Sep 12, 2023 at 03:22:32PM +0800, Jisheng Zhang wrote:
> riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
> dma coherent, so set dma-noncoherent to reflect this fact.
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> Tested-by: Drew Fustini <dfustini@baylibre.com>
> ---
> 
> Since v1:
>  - rebase on v6.6-rc1
>  - collect Tested-by tag

Does this mean you're expecting me to take this?

> 
>  arch/riscv/boot/dts/thead/th1520.dtsi | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index ce708183b6f6..ff364709a6df 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -139,6 +139,7 @@ soc {
>  		interrupt-parent = <&plic>;
>  		#address-cells = <2>;
>  		#size-cells = <2>;
> +		dma-noncoherent;
>  		ranges;
>  
>  		plic: interrupt-controller@ffd8000000 {
> -- 
> 2.40.1
>
Jisheng Zhang Sept. 13, 2023, 3:15 p.m. UTC | #3 
On Tue, Sep 12, 2023 at 05:27:31PM +0100, Conor Dooley wrote:
> On Tue, Sep 12, 2023 at 03:22:32PM +0800, Jisheng Zhang wrote:
> > riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
> > dma coherent, so set dma-noncoherent to reflect this fact.
> > 
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > Tested-by: Drew Fustini <dfustini@baylibre.com>
> > ---
> > 
> > Since v1:
> >  - rebase on v6.6-rc1
> >  - collect Tested-by tag
> 
> Does this mean you're expecting me to take this?

Hi Conor,

I think I will take this and send PR to soc people. The reason
I send v2 is the rebasing on new rc1 and v1 wasn't in linux-riscv
mailist due to typo;

Thank you so much
> 
> > 
> >  arch/riscv/boot/dts/thead/th1520.dtsi | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> > index ce708183b6f6..ff364709a6df 100644
> > --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> > @@ -139,6 +139,7 @@ soc {
> >  		interrupt-parent = <&plic>;
> >  		#address-cells = <2>;
> >  		#size-cells = <2>;
> > +		dma-noncoherent;
> >  		ranges;
> >  
> >  		plic: interrupt-controller@ffd8000000 {
> > -- 
> > 2.40.1
> >
Conor Dooley Sept. 13, 2023, 3:44 p.m. UTC | #4 
On Wed, Sep 13, 2023 at 11:15:57PM +0800, Jisheng Zhang wrote:
> On Tue, Sep 12, 2023 at 05:27:31PM +0100, Conor Dooley wrote:
> > On Tue, Sep 12, 2023 at 03:22:32PM +0800, Jisheng Zhang wrote:
> > > riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
> > > dma coherent, so set dma-noncoherent to reflect this fact.
> > > 
> > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > > Tested-by: Drew Fustini <dfustini@baylibre.com>
> > > ---
> > > 
> > > Since v1:
> > >  - rebase on v6.6-rc1
> > >  - collect Tested-by tag
> > 
> > Does this mean you're expecting me to take this?
> 
> Hi Conor,
> 
> I think I will take this and send PR to soc people. The reason
> I send v2 is the rebasing on new rc1 and v1 wasn't in linux-riscv
> mailist due to typo;

Great, thanks. Please ask SFR to add your tree to linux-next.

Cheers,
Conor.
Conor Dooley Sept. 20, 2023, 8:36 a.m. UTC | #5 
Hey Jisheng,

On Wed, Sep 13, 2023 at 04:44:18PM +0100, Conor Dooley wrote:
> On Wed, Sep 13, 2023 at 11:15:57PM +0800, Jisheng Zhang wrote:
> > On Tue, Sep 12, 2023 at 05:27:31PM +0100, Conor Dooley wrote:
> > > On Tue, Sep 12, 2023 at 03:22:32PM +0800, Jisheng Zhang wrote:
> > > > riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
> > > > dma coherent, so set dma-noncoherent to reflect this fact.
> > > > 
> > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > > > Tested-by: Drew Fustini <dfustini@baylibre.com>
> > > > ---
> > > > 
> > > > Since v1:
> > > >  - rebase on v6.6-rc1
> > > >  - collect Tested-by tag
> > > 
> > > Does this mean you're expecting me to take this?
> > 
> > Hi Conor,
> > 
> > I think I will take this and send PR to soc people. The reason
> > I send v2 is the rebasing on new rc1 and v1 wasn't in linux-riscv
> > mailist due to typo;
> 
> Great, thanks. Please ask SFR to add your tree to linux-next.

I lost my main x86 box over the weekend (looks like probably a dead
motherboard), so I may have missed a response to this.

Did you see this email? Additionally, can you add that git tree to the
maintainers entry for the thead devicetrees?

Thanks,
Conor.
Jisheng Zhang Sept. 21, 2023, 9:24 a.m. UTC | #6 
On Wed, Sep 20, 2023 at 09:36:19AM +0100, Conor Dooley wrote:
> Hey Jisheng,
> 
> On Wed, Sep 13, 2023 at 04:44:18PM +0100, Conor Dooley wrote:
> > On Wed, Sep 13, 2023 at 11:15:57PM +0800, Jisheng Zhang wrote:
> > > On Tue, Sep 12, 2023 at 05:27:31PM +0100, Conor Dooley wrote:
> > > > On Tue, Sep 12, 2023 at 03:22:32PM +0800, Jisheng Zhang wrote:
> > > > > riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
> > > > > dma coherent, so set dma-noncoherent to reflect this fact.
> > > > > 
> > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > > > > Tested-by: Drew Fustini <dfustini@baylibre.com>
> > > > > ---
> > > > > 
> > > > > Since v1:
> > > > >  - rebase on v6.6-rc1
> > > > >  - collect Tested-by tag
> > > > 
> > > > Does this mean you're expecting me to take this?
> > > 
> > > Hi Conor,
> > > 
> > > I think I will take this and send PR to soc people. The reason
> > > I send v2 is the rebasing on new rc1 and v1 wasn't in linux-riscv
> > > mailist due to typo;
> > 
> > Great, thanks. Please ask SFR to add your tree to linux-next.

Hi Conor,

I'm not sure how to do this. When MAINTAINERS patch is merged, send
an email to Stephen Rothwell, are these steps correct?

> 
> I lost my main x86 box over the weekend (looks like probably a dead
> motherboard), so I may have missed a response to this.
> 
> Did you see this email? Additionally, can you add that git tree to the
> maintainers entry for the thead devicetrees?

I just created a tree in
git://git.kernel.org/pub/scm/linux/kernel/git/jszhang/linux.git

But it needs time for cgit to take place. I will send a patch
once it appears.

Thanks
Conor Dooley Sept. 21, 2023, 10:08 a.m. UTC | #7 
On Thu, Sep 21, 2023 at 05:24:57PM +0800, Jisheng Zhang wrote:
> On Wed, Sep 20, 2023 at 09:36:19AM +0100, Conor Dooley wrote:
> > Hey Jisheng,
> > 
> > On Wed, Sep 13, 2023 at 04:44:18PM +0100, Conor Dooley wrote:
> > > On Wed, Sep 13, 2023 at 11:15:57PM +0800, Jisheng Zhang wrote:
> > > > On Tue, Sep 12, 2023 at 05:27:31PM +0100, Conor Dooley wrote:
> > > > > On Tue, Sep 12, 2023 at 03:22:32PM +0800, Jisheng Zhang wrote:
> > > > > > riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
> > > > > > dma coherent, so set dma-noncoherent to reflect this fact.
> > > > > > 
> > > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > > > > > Tested-by: Drew Fustini <dfustini@baylibre.com>
> > > > > > ---
> > > > > > 
> > > > > > Since v1:
> > > > > >  - rebase on v6.6-rc1
> > > > > >  - collect Tested-by tag
> > > > > 
> > > > > Does this mean you're expecting me to take this?
> > > > 
> > > > Hi Conor,
> > > > 
> > > > I think I will take this and send PR to soc people. The reason
> > > > I send v2 is the rebasing on new rc1 and v1 wasn't in linux-riscv
> > > > mailist due to typo;
> > > 
> > > Great, thanks. Please ask SFR to add your tree to linux-next.
> 
> Hi Conor,
> 
> I'm not sure how to do this. When MAINTAINERS patch is merged, send
> an email to Stephen Rothwell, are these steps correct?

Sorta, yeah. You don't need to have the MAINTAINERS patch merged first
though, just send him a link to your tree and the branch name(s) & he
will include it in linux-next.

> > I lost my main x86 box over the weekend (looks like probably a dead
> > motherboard), so I may have missed a response to this.
> > 
> > Did you see this email? Additionally, can you add that git tree to the
> > maintainers entry for the thead devicetrees?
> 
> I just created a tree in
> git://git.kernel.org/pub/scm/linux/kernel/git/jszhang/linux.git
> 
> But it needs time for cgit to take place. I will send a patch
> once it appears.

Looks to be there for me now. Thanks for doing this!
Drew Fustini Oct. 16, 2023, 5:10 p.m. UTC | #8 
On Thu, Sep 21, 2023 at 11:08:28AM +0100, Conor Dooley wrote:
> On Thu, Sep 21, 2023 at 05:24:57PM +0800, Jisheng Zhang wrote:
> > On Wed, Sep 20, 2023 at 09:36:19AM +0100, Conor Dooley wrote:
> > > Hey Jisheng,
> > > 
> > > On Wed, Sep 13, 2023 at 04:44:18PM +0100, Conor Dooley wrote:
> > > > On Wed, Sep 13, 2023 at 11:15:57PM +0800, Jisheng Zhang wrote:
> > > > > On Tue, Sep 12, 2023 at 05:27:31PM +0100, Conor Dooley wrote:
> > > > > > On Tue, Sep 12, 2023 at 03:22:32PM +0800, Jisheng Zhang wrote:
> > > > > > > riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
> > > > > > > dma coherent, so set dma-noncoherent to reflect this fact.
> > > > > > > 
> > > > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > > > > > > Tested-by: Drew Fustini <dfustini@baylibre.com>
> > > > > > > ---
> > > > > > > 
> > > > > > > Since v1:
> > > > > > >  - rebase on v6.6-rc1
> > > > > > >  - collect Tested-by tag
> > > > > > 
> > > > > > Does this mean you're expecting me to take this?
> > > > > 
> > > > > Hi Conor,
> > > > > 
> > > > > I think I will take this and send PR to soc people. The reason
> > > > > I send v2 is the rebasing on new rc1 and v1 wasn't in linux-riscv
> > > > > mailist due to typo;
> > > > 
> > > > Great, thanks. Please ask SFR to add your tree to linux-next.
> > 
> > Hi Conor,
> > 
> > I'm not sure how to do this. When MAINTAINERS patch is merged, send
> > an email to Stephen Rothwell, are these steps correct?
> 
> Sorta, yeah. You don't need to have the MAINTAINERS patch merged first
> though, just send him a link to your tree and the branch name(s) & he
> will include it in linux-next.
> 
> > > I lost my main x86 box over the weekend (looks like probably a dead
> > > motherboard), so I may have missed a response to this.
> > > 
> > > Did you see this email? Additionally, can you add that git tree to the
> > > maintainers entry for the thead devicetrees?
> > 
> > I just created a tree in
> > git://git.kernel.org/pub/scm/linux/kernel/git/jszhang/linux.git
> > 
> > But it needs time for cgit to take place. I will send a patch
> > once it appears.
> 
> Looks to be there for me now. Thanks for doing this!

Hi Jisheng, I'm writing the cover letter for v2 of my th1520 mmc series
and I am wondering if this dma-noncoherent patch is in any tree yet?

Thanks,
Drew
Jisheng Zhang Oct. 17, 2023, 4:09 p.m. UTC | #9 
On Mon, Oct 16, 2023 at 10:10:33AM -0700, Drew Fustini wrote:
> On Thu, Sep 21, 2023 at 11:08:28AM +0100, Conor Dooley wrote:
> > On Thu, Sep 21, 2023 at 05:24:57PM +0800, Jisheng Zhang wrote:
> > > On Wed, Sep 20, 2023 at 09:36:19AM +0100, Conor Dooley wrote:
> > > > Hey Jisheng,
> > > > 
> > > > On Wed, Sep 13, 2023 at 04:44:18PM +0100, Conor Dooley wrote:
> > > > > On Wed, Sep 13, 2023 at 11:15:57PM +0800, Jisheng Zhang wrote:
> > > > > > On Tue, Sep 12, 2023 at 05:27:31PM +0100, Conor Dooley wrote:
> > > > > > > On Tue, Sep 12, 2023 at 03:22:32PM +0800, Jisheng Zhang wrote:
> > > > > > > > riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
> > > > > > > > dma coherent, so set dma-noncoherent to reflect this fact.
> > > > > > > > 
> > > > > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > > > > > > > Tested-by: Drew Fustini <dfustini@baylibre.com>
> > > > > > > > ---
> > > > > > > > 
> > > > > > > > Since v1:
> > > > > > > >  - rebase on v6.6-rc1
> > > > > > > >  - collect Tested-by tag
> > > > > > > 
> > > > > > > Does this mean you're expecting me to take this?
> > > > > > 
> > > > > > Hi Conor,
> > > > > > 
> > > > > > I think I will take this and send PR to soc people. The reason
> > > > > > I send v2 is the rebasing on new rc1 and v1 wasn't in linux-riscv
> > > > > > mailist due to typo;
> > > > > 
> > > > > Great, thanks. Please ask SFR to add your tree to linux-next.
> > > 
> > > Hi Conor,
> > > 
> > > I'm not sure how to do this. When MAINTAINERS patch is merged, send
> > > an email to Stephen Rothwell, are these steps correct?
> > 
> > Sorta, yeah. You don't need to have the MAINTAINERS patch merged first
> > though, just send him a link to your tree and the branch name(s) & he
> > will include it in linux-next.
> > 
> > > > I lost my main x86 box over the weekend (looks like probably a dead
> > > > motherboard), so I may have missed a response to this.
> > > > 
> > > > Did you see this email? Additionally, can you add that git tree to the
> > > > maintainers entry for the thead devicetrees?
> > > 
> > > I just created a tree in
> > > git://git.kernel.org/pub/scm/linux/kernel/git/jszhang/linux.git
> > > 
> > > But it needs time for cgit to take place. I will send a patch
> > > once it appears.
> > 
> > Looks to be there for me now. Thanks for doing this!
> 
> Hi Jisheng, I'm writing the cover letter for v2 of my th1520 mmc series
> and I am wondering if this dma-noncoherent patch is in any tree yet?

Hi Drew,

I forget this patch. Thanks for reminding.

Hi Arnd

This is the only one dt fix for thead SoC, can you please pick it up
for the upcoming -rcN? I knew soc people can directly ask for pick
up for only one fix in the past. Let me know if I need to generate a
formal PR.

Thanks in advace
Arnd Bergmann Oct. 17, 2023, 8:33 p.m. UTC | #10 
On Tue, Oct 17, 2023, at 18:09, Jisheng Zhang wrote:
> On Mon, Oct 16, 2023 at 10:10:33AM -0700, Drew Fustini wrote:
>> On Thu, Sep 21, 2023 at 11:08:28AM +0100, Conor Dooley wrote:
>>
>> Hi Jisheng, I'm writing the cover letter for v2 of my th1520 mmc series
>> and I am wondering if this dma-noncoherent patch is in any tree yet?
>
> Hi Drew,
>
> I forget this patch. Thanks for reminding.
>
> Hi Arnd
>
> This is the only one dt fix for thead SoC, can you please pick it up
> for the upcoming -rcN? I knew soc people can directly ask for pick
> up for only one fix in the past. Let me know if I need to generate a
> formal PR.

Applied to the fixes branch now, thanks.

There is no need for a pull request if you have just a single patch.

Just a few things to consider:

- For both patches and pull requests, make sure you have soc@kernel.org
  as the primary recipient so I know that I'm the one to apply them
  and see them in https://patchwork.kernel.org/project/linux-soc/list/
  I get Cc'd on a lot of patches and would otherwise not know if you
  are looking for them to be applied or reviewed.

- Since there is no tag description, add a comment under the '---'
  line asking for the patch to be applied directly, and say if
  this is a bugfix for the current release or if it should be
  queued for the next release.

    Arnd
patchwork-bot+linux-riscv@kernel.org Nov. 12, 2023, 12:55 a.m. UTC | #11 
Hello:

This patch was applied to riscv/linux.git (fixes)
by Arnd Bergmann <arnd@arndb.de>:

On Tue, 12 Sep 2023 15:22:32 +0800 you wrote:
> riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
> dma coherent, so set dma-noncoherent to reflect this fact.
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> Tested-by: Drew Fustini <dfustini@baylibre.com>
> ---
> 
> [...]

Here is the summary with links:
  - [v2] riscv: dts: thead: set dma-noncoherent to soc bus
    https://git.kernel.org/riscv/c/759426c758c7

You are awesome, thank you!
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index ce708183b6f6..ff364709a6df 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -139,6 +139,7 @@  soc {
 		interrupt-parent = <&plic>;
 		#address-cells = <2>;
 		#size-cells = <2>;
+		dma-noncoherent;
 		ranges;
 
 		plic: interrupt-controller@ffd8000000 {