| Message ID | 20230914072159.1177582-21-zhao1.liu@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Support smp.clusters for x86 in QEMU | expand |
On 9/14/2023 2:21 AM, Zhao Liu wrote: > From: Zhao Liu <zhao1.liu@intel.com> > > CPUID[0x8000001D].EAX[bits 25:14] NumSharingCache: number of logical > processors sharing cache. > > The number of logical processors sharing this cache is > NumSharingCache + 1. > > After cache models have topology information, we can use > CPUCacheInfo.share_level to decide which topology level to be encoded > into CPUID[0x8000001D].EAX[bits 25:14]. > > Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Babu Moger <babu.moger@amd.com> > --- > Changes since v3: > * Explain what "CPUID[0x8000001D].EAX[bits 25:14]" means in the commit > message. (Babu) > > Changes since v1: > * Use cache->share_level as the parameter in > max_processor_ids_for_cache(). > --- > target/i386/cpu.c | 10 +--------- > 1 file changed, 1 insertion(+), 9 deletions(-) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index bc28c59df089..3bed823dc3b7 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -482,20 +482,12 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, > uint32_t *eax, uint32_t *ebx, > uint32_t *ecx, uint32_t *edx) > { > - uint32_t num_sharing_cache; > assert(cache->size == cache->line_size * cache->associativity * > cache->partitions * cache->sets); > > *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | > (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); > - > - /* L3 is shared among multiple cores */ > - if (cache->level == 3) { > - num_sharing_cache = 1 << apicid_die_offset(topo_info); > - } else { > - num_sharing_cache = 1 << apicid_core_offset(topo_info); > - } > - *eax |= (num_sharing_cache - 1) << 14; > + *eax |= max_processor_ids_for_cache(topo_info, cache->share_level) << 14; > > assert(cache->line_size > 0); > assert(cache->partitions > 0);
On Fri, Sep 22, 2023 at 02:27:58PM -0500, Moger, Babu wrote: > Date: Fri, 22 Sep 2023 14:27:58 -0500 > From: "Moger, Babu" <bmoger@amd.com> > Subject: Re: [PATCH v4 20/21] i386: Use CPUCacheInfo.share_level to encode > CPUID[0x8000001D].EAX[bits 25:14] > > > On 9/14/2023 2:21 AM, Zhao Liu wrote: > > From: Zhao Liu <zhao1.liu@intel.com> > > > > CPUID[0x8000001D].EAX[bits 25:14] NumSharingCache: number of logical > > processors sharing cache. > > > > The number of logical processors sharing this cache is > > NumSharingCache + 1. > > > > After cache models have topology information, we can use > > CPUCacheInfo.share_level to decide which topology level to be encoded > > into CPUID[0x8000001D].EAX[bits 25:14]. > > > > Signed-off-by: Zhao Liu <zhao1.liu@intel.com> > > Reviewed-by: Babu Moger <babu.moger@amd.com> Thanks Babu! -Zhao > > > > --- > > Changes since v3: > > * Explain what "CPUID[0x8000001D].EAX[bits 25:14]" means in the commit > > message. (Babu) > > > > Changes since v1: > > * Use cache->share_level as the parameter in > > max_processor_ids_for_cache(). > > --- > > target/i386/cpu.c | 10 +--------- > > 1 file changed, 1 insertion(+), 9 deletions(-) > > > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > > index bc28c59df089..3bed823dc3b7 100644 > > --- a/target/i386/cpu.c > > +++ b/target/i386/cpu.c > > @@ -482,20 +482,12 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, > > uint32_t *eax, uint32_t *ebx, > > uint32_t *ecx, uint32_t *edx) > > { > > - uint32_t num_sharing_cache; > > assert(cache->size == cache->line_size * cache->associativity * > > cache->partitions * cache->sets); > > *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | > > (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); > > - > > - /* L3 is shared among multiple cores */ > > - if (cache->level == 3) { > > - num_sharing_cache = 1 << apicid_die_offset(topo_info); > > - } else { > > - num_sharing_cache = 1 << apicid_core_offset(topo_info); > > - } > > - *eax |= (num_sharing_cache - 1) << 14; > > + *eax |= max_processor_ids_for_cache(topo_info, cache->share_level) << 14; > > assert(cache->line_size > 0); > > assert(cache->partitions > 0);
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index bc28c59df089..3bed823dc3b7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -482,20 +482,12 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - uint32_t num_sharing_cache; assert(cache->size == cache->line_size * cache->associativity * cache->partitions * cache->sets); *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); - - /* L3 is shared among multiple cores */ - if (cache->level == 3) { - num_sharing_cache = 1 << apicid_die_offset(topo_info); - } else { - num_sharing_cache = 1 << apicid_core_offset(topo_info); - } - *eax |= (num_sharing_cache - 1) << 14; + *eax |= max_processor_ids_for_cache(topo_info, cache->share_level) << 14; assert(cache->line_size > 0); assert(cache->partitions > 0);