| Message ID | 20230905102117.2011094-2-james.clark@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | coresight: Allow guests to be traced when FEAT_TRF and VHE are present | expand |
On Tue, Sep 05, 2023 at 11:21:14AM +0100, James Clark wrote: > Add separate definitions for ELx and EL2 as TRFCR_EL1 doesn't have CX. > This also mirrors the previous definition so no code change is required. Reviewed-by: Mark Brown <broonie@kernel.org> Matches DDI0601 2023-06.
On Tue, Sep 05, 2023 at 11:21:14AM +0100, James Clark wrote: > Add separate definitions for ELx and EL2 as TRFCR_EL1 doesn't have CX. > This also mirrors the previous definition so no code change is required. > > Signed-off-by: James Clark <james.clark@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> I assume these patches would go in via the coresight tree.
On 25/09/2023 16:59, Catalin Marinas wrote: > On Tue, Sep 05, 2023 at 11:21:14AM +0100, James Clark wrote: >> Add separate definitions for ELx and EL2 as TRFCR_EL1 doesn't have CX. >> This also mirrors the previous definition so no code change is required. >> >> Signed-off-by: James Clark <james.clark@arm.com> > > Acked-by: Catalin Marinas <catalin.marinas@arm.com> > > I assume these patches would go in via the coresight tree. Possibly, but I'm working on a V4 that combines the nVHE version and Suzuki's comment from here [1]. There will be more kvm patches in that one so I'm not sure. [1]: https://lists.linaro.org/archives/list/coresight@lists.linaro.org/message/A6OVUHKZZXJZG5MQ2T7VYHBAD6NOSBD7/
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index b481935e9314..fc9a5a09fa04 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -171,8 +171,6 @@ #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) -#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) - #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) @@ -382,7 +380,6 @@ #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) -#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) #define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4) #define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5) #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) @@ -640,15 +637,6 @@ /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ #define SYS_MPIDR_SAFE_VAL (BIT(31)) -#define TRFCR_ELx_TS_SHIFT 5 -#define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_EL2_CX BIT(3) -#define TRFCR_ELx_ExTRE BIT(1) -#define TRFCR_ELx_E0TRE BIT(0) - /* GIC Hypervisor interface registers */ /* ICH_MISR_EL2 bit definitions */ #define ICH_MISR_EOI (1 << 0) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 65866bf819c3..757d41db0aed 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2495,3 +2495,40 @@ Field 5 F Field 4 P Field 3:0 Align EndSysreg + +SysregFields TRFCR_EL2 +Res0 63:7 +UnsignedEnum 6:5 TS + 0b0000 USE_TRFCR_EL1_TS + 0b0001 VIRTUAL + 0b0010 GUEST_PHYSICAL + 0b0011 PHYSICAL +EndEnum +Res0 4 +Field 3 CX +Res0 2 +Field 1 E2TRE +Field 0 E0HTRE +EndSysregFields + +# TRFCR_EL1 doesn't have the CX bit so redefine it without CX instead of +# using a shared definition between TRFCR_EL2 and TRFCR_EL1 +SysregFields TRFCR_ELx +Res0 63:7 +UnsignedEnum 6:5 TS + 0b0001 VIRTUAL + 0b0010 GUEST_PHYSICAL + 0b0011 PHYSICAL +EndEnum +Res0 4:2 +Field 1 ExTRE +Field 0 E0TRE +EndSysregFields + +Sysreg TRFCR_EL1 3 0 1 2 1 +Fields TRFCR_ELx +EndSysreg + +Sysreg TRFCR_EL2 3 4 1 2 1 +Fields TRFCR_EL2 +EndSysreg
Add separate definitions for ELx and EL2 as TRFCR_EL1 doesn't have CX. This also mirrors the previous definition so no code change is required. Signed-off-by: James Clark <james.clark@arm.com> --- arch/arm64/include/asm/sysreg.h | 12 ----------- arch/arm64/tools/sysreg | 37 +++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 12 deletions(-)