diff mbox series

[1/1] dmaengine: fsl-edma: fix edma4 channel enable failure on second attempt

Message ID 20230823182635.2618118-1-Frank.Li@nxp.com (mailing list archive)
State Accepted
Commit 3f4b82167a3b1f4ddb33d890f758a042ef4ceef1
Headers show
Series [1/1] dmaengine: fsl-edma: fix edma4 channel enable failure on second attempt | expand

Commit Message

Frank Li Aug. 23, 2023, 6:26 p.m. UTC
When attempting to start DMA for the second time using
fsl_edma3_enable_request(), channel never start.

CHn_MUX must have a unique value when selecting a peripheral slot in the
channel mux configuration. The only value that may overlap is source 0.
If there is an attempt to write a mux configuration value that is already
consumed by another channel, a mux configuration of 0 (SRC = 0) will be
written.

Check CHn_MUX before writing in fsl_edma3_enable_request().

Fixes: 72f5801a4e2b ("dmaengine: fsl-edma: integrate v3 support")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/dma/fsl-edma-common.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

Comments

Frank Li Sept. 19, 2023, 4:31 a.m. UTC | #1
> -----Original Message-----
> From: Frank Li <frank.li@nxp.com>
> Sent: Wednesday, August 23, 2023 1:27 PM
> To: vkoul@kernel.org
> Cc: devicetree@vger.kernel.org; dmaengine@vger.kernel.org; Frank Li
> <frank.li@nxp.com>; imx@lists.linux.dev; Joy Zou <joy.zou@nxp.com>;
> krzysztof.kozlowski+dt@linaro.org; linux-kernel@vger.kernel.org; Peng Fan
> <peng.fan@nxp.com>; robh+dt@kernel.org; Shenwei Wang
> <shenwei.wang@nxp.com>
> Subject: [PATCH 1/1] dmaengine: fsl-edma: fix edma4 channel enable failure
> on second attempt
> 
> When attempting to start DMA for the second time using
> fsl_edma3_enable_request(), channel never start.
> 
> CHn_MUX must have a unique value when selecting a peripheral slot in the
> channel mux configuration. The only value that may overlap is source 0.
> If there is an attempt to write a mux configuration value that is already
> consumed by another channel, a mux configuration of 0 (SRC = 0) will be
> written.
> 
> Check CHn_MUX before writing in fsl_edma3_enable_request().
> 
> Fixes: 72f5801a4e2b ("dmaengine: fsl-edma: integrate v3 support")
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---

@vinod: 
	ping 

>  drivers/dma/fsl-edma-common.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-
> common.c
> index a0f5741abcc4..edb92fa93315 100644
> --- a/drivers/dma/fsl-edma-common.c
> +++ b/drivers/dma/fsl-edma-common.c
> @@ -92,8 +92,14 @@ static void fsl_edma3_enable_request(struct
> fsl_edma_chan *fsl_chan)
> 
>  	edma_writel_chreg(fsl_chan, val, ch_sbr);
> 
> -	if (flags & FSL_EDMA_DRV_HAS_CHMUX)
> -		edma_writel_chreg(fsl_chan, fsl_chan->srcid, ch_mux);
> +	if (flags & FSL_EDMA_DRV_HAS_CHMUX) {
> +		/*
> +		 * ch_mux: With the exception of 0, attempts to write a value
> +		 * already in use will be forced to 0.
> +		 */
> +		if (!edma_readl_chreg(fsl_chan, ch_mux))
> +			edma_writel_chreg(fsl_chan, fsl_chan->srcid,
> ch_mux);
> +	}
> 
>  	val = edma_readl_chreg(fsl_chan, ch_csr);
>  	val |= EDMA_V3_CH_CSR_ERQ;
> --
> 2.34.1
Vinod Koul Sept. 28, 2023, 12:08 p.m. UTC | #2
On Wed, 23 Aug 2023 14:26:35 -0400, Frank Li wrote:
> When attempting to start DMA for the second time using
> fsl_edma3_enable_request(), channel never start.
> 
> CHn_MUX must have a unique value when selecting a peripheral slot in the
> channel mux configuration. The only value that may overlap is source 0.
> If there is an attempt to write a mux configuration value that is already
> consumed by another channel, a mux configuration of 0 (SRC = 0) will be
> written.
> 
> [...]

Applied, thanks!

[1/1] dmaengine: fsl-edma: fix edma4 channel enable failure on second attempt
      commit: 3f4b82167a3b1f4ddb33d890f758a042ef4ceef1

Best regards,
diff mbox series

Patch

diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index a0f5741abcc4..edb92fa93315 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -92,8 +92,14 @@  static void fsl_edma3_enable_request(struct fsl_edma_chan *fsl_chan)
 
 	edma_writel_chreg(fsl_chan, val, ch_sbr);
 
-	if (flags & FSL_EDMA_DRV_HAS_CHMUX)
-		edma_writel_chreg(fsl_chan, fsl_chan->srcid, ch_mux);
+	if (flags & FSL_EDMA_DRV_HAS_CHMUX) {
+		/*
+		 * ch_mux: With the exception of 0, attempts to write a value
+		 * already in use will be forced to 0.
+		 */
+		if (!edma_readl_chreg(fsl_chan, ch_mux))
+			edma_writel_chreg(fsl_chan, fsl_chan->srcid, ch_mux);
+	}
 
 	val = edma_readl_chreg(fsl_chan, ch_csr);
 	val |= EDMA_V3_CH_CSR_ERQ;