mbox

[PULL,v2,00/21] tricore queue

Message ID 20230928085303.511518-1-kbastian@mail.uni-paderborn.de (mailing list archive)
State New, archived
Headers show

Pull-request

https://github.com/bkoppelmann/qemu.git tags/pull-tricore-20230928

Message

Bastian Koppelmann Sept. 28, 2023, 8:52 a.m. UTC 
The following changes since commit 36e9aab3c569d4c9ad780473596e18479838d1aa:

  migration: Move return path cleanup to main migration thread (2023-09-27 13:58:02 -0400)

are available in the Git repository at:

  https://github.com/bkoppelmann/qemu.git tags/pull-tricore-20230928

for you to fetch changes up to 080ca1baa84316a58790b6507de89fabf4c40ec0:

  target/tricore: Change effective address (ea) to target_ulong (2023-09-28 10:45:22 +0200)

----------------------------------------------------------------
- Add FTOU, CRCN, FTOHP, and HPTOF insns
- Add test for arithmetic TriCore insns

----------------------------------------------------------------
Changes from v1:
- Removed sas.py file that slipped in patch 15
----------------------------------------------------------------

Bastian Koppelmann (21):
      tests/tcg/tricore: Bump cpu to tc37x
      target/tricore: Implement CRCN insn
      target/tricore: Correctly handle FPU RM from PSW
      target/tricore: Implement FTOU insn
      target/tricore: Clarify special case for FTOUZ insn
      target/tricore: Implement ftohp insn
      target/tricore: Implement hptof insn
      target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0
      target/tricore: Swap src and dst reg for RCRR_INSERT
      target/tricore: Replace cpu_*_code with translator_*
      target/tricore: Fix FTOUZ being ISA v1.3.1 up
      tests/tcg/tricore: Extended and non-extened regs now match
      hw/tricore: Log failing test in testdevice
      tests/tcg: Reset result register after each test
      tests/tcg/tricore: Add test for all arith insns up to addx
      tests/tcg/tricore: Add test from 'and' to 'csub'
      tests/tcg/tricore: Add test from 'dextr' to 'lt'
      tests/tcg/tricore: Add test from 'max' to 'shas'
      tests/tcg/tricore: Add test from 'shuffle' to 'xor.t'
      target/tricore: Remove CSFRs from cpu.h
      target/tricore: Change effective address (ea) to target_ulong

 hw/tricore/tricore_testdevice.c           |   4 +
 target/tricore/cpu.h                      | 143 +--------------
 target/tricore/fpu_helper.c               | 111 ++++++++++++
 target/tricore/helper.c                   |  19 +-
 target/tricore/helper.h                   |   4 +
 target/tricore/op_helper.c                |  79 ++++++++-
 target/tricore/translate.c                |  56 ++++--
 target/tricore/tricore-opcodes.h          |   3 +
 tests/tcg/tricore/Makefile.softmmu-target |   7 +-
 tests/tcg/tricore/asm/macros.h            | 190 +++++++++++++++++---
 tests/tcg/tricore/asm/test_arith.S        | 280 ++++++++++++++++++++++++++++++
 tests/tcg/tricore/asm/test_crcn.S         |   9 +
 tests/tcg/tricore/asm/test_ftohp.S        |  14 ++
 tests/tcg/tricore/asm/test_ftou.S         |  12 ++
 tests/tcg/tricore/asm/test_hptof.S        |  12 ++
 tests/tcg/tricore/asm/test_insert.S       |  14 ++
 16 files changed, 780 insertions(+), 177 deletions(-)
 create mode 100644 tests/tcg/tricore/asm/test_arith.S
 create mode 100644 tests/tcg/tricore/asm/test_crcn.S
 create mode 100644 tests/tcg/tricore/asm/test_ftohp.S
 create mode 100644 tests/tcg/tricore/asm/test_ftou.S
 create mode 100644 tests/tcg/tricore/asm/test_hptof.S

Comments

Stefan Hajnoczi Sept. 28, 2023, 2:26 p.m. UTC | #1 
Please take a look at these CI test failures:
https://gitlab.com/qemu-project/qemu/-/jobs/5185201978
https://gitlab.com/qemu-project/qemu/-/jobs/5185202098

Thanks,
Stefan

On Thu, 28 Sept 2023 at 04:57, Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
>
> The following changes since commit 36e9aab3c569d4c9ad780473596e18479838d1aa:
>
>   migration: Move return path cleanup to main migration thread (2023-09-27 13:58:02 -0400)
>
> are available in the Git repository at:
>
>   https://github.com/bkoppelmann/qemu.git tags/pull-tricore-20230928
>
> for you to fetch changes up to 080ca1baa84316a58790b6507de89fabf4c40ec0:
>
>   target/tricore: Change effective address (ea) to target_ulong (2023-09-28 10:45:22 +0200)
>
> ----------------------------------------------------------------
> - Add FTOU, CRCN, FTOHP, and HPTOF insns
> - Add test for arithmetic TriCore insns
>
> ----------------------------------------------------------------
> Changes from v1:
> - Removed sas.py file that slipped in patch 15
> ----------------------------------------------------------------
>
> Bastian Koppelmann (21):
>       tests/tcg/tricore: Bump cpu to tc37x
>       target/tricore: Implement CRCN insn
>       target/tricore: Correctly handle FPU RM from PSW
>       target/tricore: Implement FTOU insn
>       target/tricore: Clarify special case for FTOUZ insn
>       target/tricore: Implement ftohp insn
>       target/tricore: Implement hptof insn
>       target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0
>       target/tricore: Swap src and dst reg for RCRR_INSERT
>       target/tricore: Replace cpu_*_code with translator_*
>       target/tricore: Fix FTOUZ being ISA v1.3.1 up
>       tests/tcg/tricore: Extended and non-extened regs now match
>       hw/tricore: Log failing test in testdevice
>       tests/tcg: Reset result register after each test
>       tests/tcg/tricore: Add test for all arith insns up to addx
>       tests/tcg/tricore: Add test from 'and' to 'csub'
>       tests/tcg/tricore: Add test from 'dextr' to 'lt'
>       tests/tcg/tricore: Add test from 'max' to 'shas'
>       tests/tcg/tricore: Add test from 'shuffle' to 'xor.t'
>       target/tricore: Remove CSFRs from cpu.h
>       target/tricore: Change effective address (ea) to target_ulong
>
>  hw/tricore/tricore_testdevice.c           |   4 +
>  target/tricore/cpu.h                      | 143 +--------------
>  target/tricore/fpu_helper.c               | 111 ++++++++++++
>  target/tricore/helper.c                   |  19 +-
>  target/tricore/helper.h                   |   4 +
>  target/tricore/op_helper.c                |  79 ++++++++-
>  target/tricore/translate.c                |  56 ++++--
>  target/tricore/tricore-opcodes.h          |   3 +
>  tests/tcg/tricore/Makefile.softmmu-target |   7 +-
>  tests/tcg/tricore/asm/macros.h            | 190 +++++++++++++++++---
>  tests/tcg/tricore/asm/test_arith.S        | 280 ++++++++++++++++++++++++++++++
>  tests/tcg/tricore/asm/test_crcn.S         |   9 +
>  tests/tcg/tricore/asm/test_ftohp.S        |  14 ++
>  tests/tcg/tricore/asm/test_ftou.S         |  12 ++
>  tests/tcg/tricore/asm/test_hptof.S        |  12 ++
>  tests/tcg/tricore/asm/test_insert.S       |  14 ++
>  16 files changed, 780 insertions(+), 177 deletions(-)
>  create mode 100644 tests/tcg/tricore/asm/test_arith.S
>  create mode 100644 tests/tcg/tricore/asm/test_crcn.S
>  create mode 100644 tests/tcg/tricore/asm/test_ftohp.S
>  create mode 100644 tests/tcg/tricore/asm/test_ftou.S
>  create mode 100644 tests/tcg/tricore/asm/test_hptof.S
>
Bastian Koppelmann Sept. 29, 2023, 6:38 a.m. UTC | #2 
Hi,

On Thu, Sep 28, 2023 at 10:26:18AM -0400, Stefan Hajnoczi wrote:
> Please take a look at these CI test failures:
> https://gitlab.com/qemu-project/qemu/-/jobs/5185201978
> https://gitlab.com/qemu-project/qemu/-/jobs/5185202098

I'll fix the build failure and drop the patches that fail the TriCore asm tests.

Cheers,
Bastian