[PULL,v3,00/16] tricore queue

Pull-request

https://github.com/bkoppelmann/qemu.git tags/pull-tricore-20230929

Message

Bastian Koppelmann Sept. 29, 2023, 6:39 a.m. UTC

The following changes since commit 36e9aab3c569d4c9ad780473596e18479838d1aa:

  migration: Move return path cleanup to main migration thread (2023-09-27 13:58:02 -0400)

are available in the Git repository at:

  https://github.com/bkoppelmann/qemu.git tags/pull-tricore-20230929

for you to fetch changes up to ceada000846b0cd81c578b1da9f76d0c59536654:

  target/tricore: Change effective address (ea) to target_ulong (2023-09-29 08:28:09 +0200)

----------------------------------------------------------------
- Add FTOU, CRCN, FTOHP, and HPTOF insns

----------------------------------------------------------------
Changes from v2:
- Replaced %ld with PRIu64 for patch 13
- Dropped patches 15 - 19, as they require an updated patch series
----------------------------------------------------------------

Bastian Koppelmann (16):
      tests/tcg/tricore: Bump cpu to tc37x
      target/tricore: Implement CRCN insn
      target/tricore: Correctly handle FPU RM from PSW
      target/tricore: Implement FTOU insn
      target/tricore: Clarify special case for FTOUZ insn
      target/tricore: Implement ftohp insn
      target/tricore: Implement hptof insn
      target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0
      target/tricore: Swap src and dst reg for RCRR_INSERT
      target/tricore: Replace cpu_*_code with translator_*
      target/tricore: Fix FTOUZ being ISA v1.3.1 up
      tests/tcg/tricore: Extended and non-extened regs now match
      hw/tricore: Log failing test in testdevice
      tests/tcg: Reset result register after each test
      target/tricore: Remove CSFRs from cpu.h
      target/tricore: Change effective address (ea) to target_ulong

 hw/tricore/tricore_testdevice.c           |   4 +
 target/tricore/cpu.h                      | 143 ++----------------------------
 target/tricore/fpu_helper.c               | 111 +++++++++++++++++++++++
 target/tricore/helper.c                   |  19 +++-
 target/tricore/helper.h                   |   4 +
 target/tricore/op_helper.c                |  79 +++++++++++++++--
 target/tricore/translate.c                |  56 +++++++++---
 target/tricore/tricore-opcodes.h          |   3 +
 tests/tcg/tricore/Makefile.softmmu-target |   6 +-
 tests/tcg/tricore/asm/macros.h            |  65 +++++++++-----
 tests/tcg/tricore/asm/test_crcn.S         |   9 ++
 tests/tcg/tricore/asm/test_ftohp.S        |  14 +++
 tests/tcg/tricore/asm/test_ftou.S         |  12 +++
 tests/tcg/tricore/asm/test_hptof.S        |  12 +++
 tests/tcg/tricore/asm/test_insert.S       |  14 +++
 15 files changed, 376 insertions(+), 175 deletions(-)
 create mode 100644 tests/tcg/tricore/asm/test_crcn.S
 create mode 100644 tests/tcg/tricore/asm/test_ftohp.S
 create mode 100644 tests/tcg/tricore/asm/test_ftou.S
 create mode 100644 tests/tcg/tricore/asm/test_hptof.S

Comments

Stefan Hajnoczi Oct. 2, 2023, 9:56 p.m. UTC | #1

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes.

Michael Tokarev Oct. 2, 2023, 11:06 p.m. UTC | #2

29.09.2023 09:39, Bastian Koppelmann:

> ----------------------------------------------------------------
> - Add FTOU, CRCN, FTOHP, and HPTOF insns
> 
> ----------------------------------------------------------------
> Changes from v2:
> - Replaced %ld with PRIu64 for patch 13
> - Dropped patches 15 - 19, as they require an updated patch series
> ----------------------------------------------------------------
> 
> Bastian Koppelmann (16):
>        tests/tcg/tricore: Bump cpu to tc37x
>        target/tricore: Implement CRCN insn
>        target/tricore: Correctly handle FPU RM from PSW
>        target/tricore: Implement FTOU insn
>        target/tricore: Clarify special case for FTOUZ insn
>        target/tricore: Implement ftohp insn
>        target/tricore: Implement hptof insn
>        target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0
>        target/tricore: Swap src and dst reg for RCRR_INSERT
>        target/tricore: Replace cpu_*_code with translator_*
>        target/tricore: Fix FTOUZ being ISA v1.3.1 up
>        tests/tcg/tricore: Extended and non-extened regs now match
>        hw/tricore: Log failing test in testdevice
>        tests/tcg: Reset result register after each test
>        target/tricore: Remove CSFRs from cpu.h
>        target/tricore: Change effective address (ea) to target_ulong

Is there anything here to apply to -stable, or there's no reason to bother?
"Fix RCPW/RRPW_INSERT insns for width = 0" might be a candidate, maybe others..

Thanks,

/mjt