| Message ID | 20230914093027.3901602-1-w.egorov@phytec.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: ti: phycore-am64: Add RTC interrupt pin | expand |
Hi Wadim Egorov, On Thu, 14 Sep 2023 11:30:27 +0200, Wadim Egorov wrote: > Wth commit 16b26f602758 ("rtc: rv3028: Use IRQ flags obtained from device > tree if available") we can now use the interrupt pin of the RTC. > Let's add interrupt pin definitions to the SoM RTC. > > I have applied the following to branch ti-k3-dts-next on [1]. Thank you! [1/1] arm64: dts: ti: phycore-am64: Add RTC interrupt pin commit: a1cd710f56c145bc7e7fc2bfbe332d944d5338cd All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent up the chain during the next merge window (or sooner if it is a relevant bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. [1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git -- Vignesh
diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index 1c2c8f0daca9..f87f09d83c95 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -126,6 +126,12 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ >; }; + + rtc_pins_default: rtc-defaults-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* (C19) EXTINTn.GPIO1_70 */ + >; + }; }; &cpsw3g { @@ -177,6 +183,11 @@ eeprom@50 { i2c_som_rtc: rtc@52 { compatible = "microcrystal,rv3028"; reg = <0x52>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_pins_default>; + interrupt-parent = <&main_gpio1>; + interrupts = <70 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; }; };
Wth commit 16b26f602758 ("rtc: rv3028: Use IRQ flags obtained from device tree if available") we can now use the interrupt pin of the RTC. Let's add interrupt pin definitions to the SoM RTC. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> --- arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)