[1/5] riscv: dts: renesas: r9a07g043f: Add L2 cache node

Commit Message

Lad, Prabhakar Sept. 29, 2023, 12:07 a.m. UTC

From: Lad Prabhakar <[e-mail]>

Add L2 cache node for RZ/Five SoC.

Signed-off-by: Lad Prabhakar <[e-mail]>
---
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Comments

Geert Uytterhoeven Oct. 3, 2023, 12:23 p.m. UTC | #1

On Fri, Sep 29, 2023 at 2:07 AM Prabhakar <[e-mail]> wrote:
> From: Lad Prabhakar <[e-mail]>
>
> Add L2 cache node for RZ/Five SoC.
>
> Signed-off-by: Lad Prabhakar <[e-mail]>

Reviewed-by: Geert Uytterhoeven <[e-mail]>
i.e. will queue in renesas-devel for v6.7.

Gr{oetje,eeting}s,

                        Geert

Patch

diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index 6ec1c6f9a403..c8d63a8f7d86 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -29,6 +29,7 @@  cpu0: cpu@0 {
 			i-cache-line-size = <0x40>;
 			d-cache-size = <0x8000>;
 			d-cache-line-size = <0x40>;
+			next-level-cache = <&l2cache>;
 			clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
 			operating-points-v2 = <&cluster0_opp>;
 
@@ -56,4 +57,15 @@  plic: interrupt-controller@12c00000 {
 		resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
 		interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
 	};
+
+	l2cache: cache-controller@13400000 {
+		compatible = "andestech,ax45mp-cache", "cache";
+		reg = <0x0 0x13400000 0x0 0x100000>;
+		interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
+		cache-size = <0x40000>;
+		cache-line-size = <64>;
+		cache-sets = <1024>;
+		cache-unified;
+		cache-level = <2>;
+	};
 };