[2/5] riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property

Commit Message

Lad, Prabhakar Sept. 29, 2023, 12:07 a.m. UTC

From: Lad Prabhakar <[e-mail]>

RZ/Five is a noncoherent SoC so to indicate this add dma-noncoherent
property to RZ/Five SoC DTSI.

Signed-off-by: Lad Prabhakar <[e-mail]>
---
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 1 +
 1 file changed, 1 insertion(+)

Comments

Geert Uytterhoeven Oct. 3, 2023, 12:24 p.m. UTC | #1

On Fri, Sep 29, 2023 at 2:07 AM Prabhakar <[e-mail]> wrote:
> From: Lad Prabhakar <[e-mail]>
>
> RZ/Five is a noncoherent SoC so to indicate this add dma-noncoherent
> property to RZ/Five SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <[e-mail]>

Reviewed-by: Geert Uytterhoeven <[e-mail]>
i.e. will queue in renesas-devel for v6.7.

Gr{oetje,eeting}s,

                        Geert

Patch

diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index c8d63a8f7d86..b0796015e36b 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -43,6 +43,7 @@  cpu0_intc: interrupt-controller {
 };
 
 &soc {
+	dma-noncoherent;
 	interrupt-parent = <&plic>;
 
 	plic: interrupt-controller@12c00000 {