| Message ID | 20231004151405.521596-6-cleger@rivosinc.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | bc38f61313d316d74c16ce7287d6dba2f42502c9 |
| Headers | show |
| Series | Add support to handle misaligned accesses in S-mode | expand |
Clément Léger <cleger@rivosinc.com> writes: > This sysctl tuning option allows the user to disable misaligned access > handling globally on the system. This will also be used by misaligned > detection code to temporarily disable misaligned access handling. > > Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Björn Töpel <bjorn@rivosinc.com>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6e167358a897..1313f83bb0cb 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -638,6 +638,7 @@ config THREAD_SIZE_ORDER config RISCV_MISALIGNED bool "Support misaligned load/store traps for kernel and userspace" + select SYSCTL_ARCH_UNALIGN_ALLOW default y help Say Y here if you want the kernel to embed support for misaligned diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 041fd2dbd955..b5fb1ff078e3 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -396,6 +396,9 @@ union reg_data { u64 data_u64; }; +/* sysctl hooks */ +int unaligned_enabled __read_mostly = 1; /* Enabled by default */ + int handle_misaligned_load(struct pt_regs *regs) { union reg_data val; @@ -406,6 +409,9 @@ int handle_misaligned_load(struct pt_regs *regs) perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); + if (!unaligned_enabled) + return -1; + if (get_insn(regs, epc, &insn)) return -1; @@ -502,6 +508,9 @@ int handle_misaligned_store(struct pt_regs *regs) perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); + if (!unaligned_enabled) + return -1; + if (get_insn(regs, epc, &insn)) return -1;
This sysctl tuning option allows the user to disable misaligned access handling globally on the system. This will also be used by misaligned detection code to temporarily disable misaligned access handling. Signed-off-by: Clément Léger <cleger@rivosinc.com> --- arch/riscv/Kconfig | 1 + arch/riscv/kernel/traps_misaligned.c | 9 +++++++++ 2 files changed, 10 insertions(+)