| Message ID | 20230929202436.2850388-1-jithu.joseph@intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | IFS support for GNR and SRF | expand |
On 9/29/2023 1:24 PM, Jithu Joseph wrote: > Changes in v3 > Ilpo Jarvinen > - Added Reviewed-by tags wherever provided > - In function validate_ifs_metadata() (patch 6) > - Add != 0 to next line for clarity > - In function ifs_load_firmware() (patch 5) > - return -EINVAL instead of -BADFD > - In function ifs_test_core() (patch 4) > - initialize activate.gen0.rsvd = 0 > - use if instead of conditional operator > - alignment change in ifs_scan_hashes_status_gen2 (patch 3) > Since the suggested changes from v3 are minimal, I am sending just the 3 modified patches in this v3 thread itself. Hans let me know if you want me to send a v4. Jithu
On Wed, 4 Oct 2023, Joseph, Jithu wrote: > > > On 9/29/2023 1:24 PM, Jithu Joseph wrote: > > Changes in v3 > > Ilpo Jarvinen > > - Added Reviewed-by tags wherever provided > > - In function validate_ifs_metadata() (patch 6) > > - Add != 0 to next line for clarity > > - In function ifs_load_firmware() (patch 5) > > - return -EINVAL instead of -BADFD > > - In function ifs_test_core() (patch 4) > > - initialize activate.gen0.rsvd = 0 > > - use if instead of conditional operator > > - alignment change in ifs_scan_hashes_status_gen2 (patch 3) > > > > Since the suggested changes from v3 are minimal, I am sending just the 3 modified patches > in this v3 thread itself. > > Hans let me know if you want me to send a v4. I'm taking care of 6.7 cycle (or begun from -rc3 onwards to be precise), not Hans. Please send a full v4 please because I want to give lkp an opportunity to test the whole series (even if I think the patches look okay).
On 10/5/2023 3:51 AM, Ilpo Järvinen wrote: > On Wed, 4 Oct 2023, Joseph, Jithu wrote: > >> >> >> On 9/29/2023 1:24 PM, Jithu Joseph wrote: >>> Changes in v3 >>> Ilpo Jarvinen >>> - Added Reviewed-by tags wherever provided >>> - In function validate_ifs_metadata() (patch 6) >>> - Add != 0 to next line for clarity >>> - In function ifs_load_firmware() (patch 5) >>> - return -EINVAL instead of -BADFD >>> - In function ifs_test_core() (patch 4) >>> - initialize activate.gen0.rsvd = 0 >>> - use if instead of conditional operator >>> - alignment change in ifs_scan_hashes_status_gen2 (patch 3) >>> >> >> Since the suggested changes from v3 are minimal, I am sending just the 3 modified patches >> in this v3 thread itself. >> >> Hans let me know if you want me to send a v4. > > I'm taking care of 6.7 cycle (or begun from -rc3 onwards to be precise), > not Hans. Thanks for doing this > > Please send a full v4 please because I want to give lkp an opportunity to > test the whole series (even if I think the patches look okay). > Sent the v4 series Jithu
Changes in v3 Ilpo Jarvinen - Added Reviewed-by tags wherever provided - In function validate_ifs_metadata() (patch 6) - Add != 0 to next line for clarity - In function ifs_load_firmware() (patch 5) - return -EINVAL instead of -BADFD - In function ifs_test_core() (patch 4) - initialize activate.gen0.rsvd = 0 - use if instead of conditional operator - alignment change in ifs_scan_hashes_status_gen2 (patch 3) v2 submission Link: https://lore.kernel.org/lkml/20230922232606.1928026-1-jithu.joseph@intel.com/ Changes in v2 Ilpo Jarvinen - Use GENMASK_ULL() / FIELD_GET() for bitops (patch 01) - Avoid mixing u8 type and bitfields in certain MSR structure scenarios (patch03 also suggested by Dave Hansen) - Expand bitfield structures to use consistent genx naming (patch 04) - Replace goto with do / while (patch 03) - general formatting (multiple patches) - remove un-necessary parenthesis - reformat commit message to use whole allowed 72 columns - alignment changes Other change - fold v1 04/10 and 05/10 into v2 patch 04/09 to satisfy build constraints due to consistent genx naming v1 submission: Link: https://lore.kernel.org/lkml/20230913183348.1349409-1-jithu.joseph@intel.com/ This series adds In Field Scan(IFS) support for newer CPUs like Granite Rapids(GNR) and Sierra Forest(SRF). There are changes in the IFS image loading and test flow to support these new CPUs. Note to reviewers: - patch 1/9 adds a bit mask to arch/x86/.../msr-index.h, hence x86 maintainers are cc-d. - patch 4/9 modifies an existing tracepoint, cc Steven Rostedt - Rest are localized to IFS driver Jithu Joseph (9): platform/x86/intel/ifs: Store IFS generation number platform/x86/intel/ifs: Refactor image loading code platform/x86/intel/ifs: Gen2 scan image loading platform/x86/intel/ifs: Gen2 Scan test support platform/x86/intel/ifs: Validate image size platform/x86/intel/ifs: Metadata validation for start_chunk platform/x86/intel/ifs: Add new CPU support platform/x86/intel/ifs: Add new error code platform/x86/intel/ifs: ARRAY BIST for Sierra Forest arch/x86/include/asm/msr-index.h | 1 + drivers/platform/x86/intel/ifs/ifs.h | 61 ++++++++- include/trace/events/intel_ifs.h | 16 +-- drivers/platform/x86/intel/ifs/core.c | 15 ++- drivers/platform/x86/intel/ifs/load.c | 158 +++++++++++++++++++++-- drivers/platform/x86/intel/ifs/runtest.c | 72 +++++++++-- 6 files changed, 283 insertions(+), 40 deletions(-) base-commit: 6465e260f48790807eef06b583b38ca9789b6072