diff mbox series

[v2,6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree

Message ID IA1PR20MB4953262ABB6EFFBC4B4F932BBBCEA@IA1PR20MB4953.namprd20.prod.outlook.com (mailing list archive)
State Superseded
Headers show
Series Add Huashan Pi board support | expand

Checks

Context Check Description
conchuod/vmtest-fixes-PR fail merge-conflict

Commit Message

Inochi Amaoto Oct. 9, 2023, 11:26 a.m. UTC 
Add initial device tree for the CV1812H RISC-V SoC by SOPHGO.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
---
 arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 36 +++++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi

--
2.42.0

Comments

Chen Wang Oct. 10, 2023, 7:21 a.m. UTC | #1 
On 2023/10/9 19:26, Inochi Amaoto wrote:
> Add initial device tree for the CV1812H RISC-V SoC by SOPHGO.
>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> ---
>   arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 36 +++++++++++++++++++++++++
>   1 file changed, 36 insertions(+)
>   create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> new file mode 100644
> index 000000000000..3864d34b0100
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> @@ -0,0 +1,36 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
This include is not required.
> +#include "cv180x.dtsi"
> +
> +/ {
> +	compatible = "sophgo,cv1812h";
> +
> +	memory@80000000 {
> +		device_type = "memory";
> +		reg = <0x80000000 0x10000000>;
> +	};
What's this defined for , I see this is different against cv1800b.
> +
> +	soc {
> +		interrupt-parent = <&plic>;
> +
> +		plic: interrupt-controller@70000000 {
> +			compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
> +			reg = <0x70000000 0x4000000>;
> +			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> +			interrupt-controller;
> +			#address-cells = <0>;
> +			#interrupt-cells = <2>;
> +			riscv,ndev = <101>;
> +		};
> +
> +		clint: timer@74000000 {
> +			compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
> +			reg = <0x74000000 0x10000>;
> +			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> +		};
> +	};
> +};
> --
> 2.42.0
>
Inochi Amaoto Oct. 10, 2023, 7:53 a.m. UTC | #2 
>On 2023/10/9 19:26, Inochi Amaoto wrote:
>> Add initial device tree for the CV1812H RISC-V SoC by SOPHGO.
>>
>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
>> ---
>>   arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 36 +++++++++++++++++++++++++
>>   1 file changed, 36 insertions(+)
>>   create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi
>>
>> diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
>> new file mode 100644
>> index 000000000000..3864d34b0100
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
>> @@ -0,0 +1,36 @@
>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> +/*
>> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/irq.h>
>This include is not required.

Thx.

>> +#include "cv180x.dtsi"
>> +
>> +/ {
>> +    compatible = "sophgo,cv1812h";
>> +
>> +    memory@80000000 {
>> +        device_type = "memory";
>> +        reg = <0x80000000 0x10000000>;
>> +    };
>What's this defined for , I see this is different against cv1800b.

CV1812h have a embedded 256MB RAM. The cv1800b is 64MB, This is why the
size is different. I write this node here because the RAM is embedded
and fixed size, and leave it in the board DT is unnecessary.

>> +
>> +    soc {
>> +        interrupt-parent = <&plic>;
>> +
>> +        plic: interrupt-controller@70000000 {
>> +            compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
>> +            reg = <0x70000000 0x4000000>;
>> +            interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
>> +            interrupt-controller;
>> +            #address-cells = <0>;
>> +            #interrupt-cells = <2>;
>> +            riscv,ndev = <101>;
>> +        };
>> +
>> +        clint: timer@74000000 {
>> +            compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
>> +            reg = <0x74000000 0x10000>;
>> +            interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
>> +        };
>> +    };
>> +};
>> --
>> 2.42.0
>>
>
Conor Dooley Oct. 12, 2023, 9:41 a.m. UTC | #3 
On Tue, Oct 10, 2023 at 03:53:54PM +0800, Inochi Amaoto wrote:
> >On 2023/10/9 19:26, Inochi Amaoto wrote:
> >> Add initial device tree for the CV1812H RISC-V SoC by SOPHGO.
> >>
> >> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> >> ---
> >>   arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 36 +++++++++++++++++++++++++
> >>   1 file changed, 36 insertions(+)
> >>   create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> >>
> >> diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> >> new file mode 100644
> >> index 000000000000..3864d34b0100
> >> --- /dev/null
> >> +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> >> @@ -0,0 +1,36 @@
> >> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >> +/*
> >> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
> >> + */
> >> +
> >> +#include <dt-bindings/interrupt-controller/irq.h>
> >This include is not required.
> 
> Thx.

I can drop this include on application. Is the rest of the series okay
with you Chen Wang?

Thanks,
Conor.

> 
> >> +#include "cv180x.dtsi"
> >> +
> >> +/ {
> >> +    compatible = "sophgo,cv1812h";
> >> +
> >> +    memory@80000000 {
> >> +        device_type = "memory";
> >> +        reg = <0x80000000 0x10000000>;
> >> +    };
> >What's this defined for , I see this is different against cv1800b.
> 
> CV1812h have a embedded 256MB RAM. The cv1800b is 64MB, This is why the
> size is different. I write this node here because the RAM is embedded
> and fixed size, and leave it in the board DT is unnecessary.
> 
> >> +
> >> +    soc {
> >> +        interrupt-parent = <&plic>;
> >> +
> >> +        plic: interrupt-controller@70000000 {
> >> +            compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
> >> +            reg = <0x70000000 0x4000000>;
> >> +            interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> >> +            interrupt-controller;
> >> +            #address-cells = <0>;
> >> +            #interrupt-cells = <2>;
> >> +            riscv,ndev = <101>;
> >> +        };
> >> +
> >> +        clint: timer@74000000 {
> >> +            compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
> >> +            reg = <0x74000000 0x10000>;
> >> +            interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> >> +        };
> >> +    };
> >> +};
> >> --
> >> 2.42.0
> >>
> >
Chen Wang Oct. 12, 2023, 1:02 p.m. UTC | #4 
On 2023/10/12 17:41, Conor Dooley wrote:
> On Tue, Oct 10, 2023 at 03:53:54PM +0800, Inochi Amaoto wrote:
>>> On 2023/10/9 19:26, Inochi Amaoto wrote:
>>>> Add initial device tree for the CV1812H RISC-V SoC by SOPHGO.
>>>>
>>>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
>>>> ---
>>>>    arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 36 +++++++++++++++++++++++++
>>>>    1 file changed, 36 insertions(+)
>>>>    create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi
>>>>
>>>> diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
>>>> new file mode 100644
>>>> index 000000000000..3864d34b0100
>>>> --- /dev/null
>>>> +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
>>>> @@ -0,0 +1,36 @@
>>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>>> +/*
>>>> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
>>>> + */
>>>> +
>>>> +#include <dt-bindings/interrupt-controller/irq.h>
>>> This include is not required.
>> Thx.
> I can drop this include on application. Is the rest of the series okay
> with you Chen Wang?
>
> Thanks,
> Conor.

Yes, just remove this include and the others are all

Acked-by: Chen Wang <unicorn_wang@outlook.com>

I also ran dtbs check with W=1 and no warning found.

BTW, due to this patchset changes some code submitted by Jisheng, I have 
sent email to him and hope he to have a look too.
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
new file mode 100644
index 000000000000..3864d34b0100
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
@@ -0,0 +1,36 @@ 
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "cv180x.dtsi"
+
+/ {
+	compatible = "sophgo,cv1812h";
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>;
+	};
+
+	soc {
+		interrupt-parent = <&plic>;
+
+		plic: interrupt-controller@70000000 {
+			compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
+			reg = <0x70000000 0x4000000>;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			riscv,ndev = <101>;
+		};
+
+		clint: timer@74000000 {
+			compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
+			reg = <0x74000000 0x10000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+		};
+	};
+};