| Message ID | IA1PR20MB49532560A3CA2670A0EAB846BBCEA@IA1PR20MB4953.namprd20.prod.outlook.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add Huashan Pi board support | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/vmtest-fixes-PR | fail | merge-conflict |
On 2023/10/9 19:26, Inochi Amaoto wrote: > Move the cpu and the common peripherals of CV181x and CV180x to new file. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > --- > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 95 +------------------ > .../dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} | 19 +--- > 2 files changed, 2 insertions(+), 112 deletions(-) > copy arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} (80%) > > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > index df40e87ee063..0904154f9829 100644 > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi Hi，Jisheng Do you have any more comment on this change related to cv1800b? > @@ -3,106 +3,13 @@ > * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > */ > > -#include <dt-bindings/interrupt-controller/irq.h> > +#include "cv180x.dtsi" > > / { > compatible = "sophgo,cv1800b"; > - #address-cells = <1>; > - #size-cells = <1>; > - > - cpus: cpus { > - #address-cells = <1>; > - #size-cells = <0>; > - timebase-frequency = <25000000>; > - > - cpu0: cpu@0 { > - compatible = "thead,c906", "riscv"; > - device_type = "cpu"; > - reg = <0>; > - d-cache-block-size = <64>; > - d-cache-sets = <512>; > - d-cache-size = <65536>; > - i-cache-block-size = <64>; > - i-cache-sets = <128>; > - i-cache-size = <32768>; > - mmu-type = "riscv,sv39"; > - riscv,isa = "rv64imafdc"; > - riscv,isa-base = "rv64i"; > - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > - "zifencei", "zihpm"; > - > - cpu0_intc: interrupt-controller { > - compatible = "riscv,cpu-intc"; > - interrupt-controller; > - #address-cells = <0>; > - #interrupt-cells = <1>; > - }; > - }; > - }; > - > - osc: oscillator { > - compatible = "fixed-clock"; > - clock-output-names = "osc_25m"; > - #clock-cells = <0>; > - }; > > soc { > - compatible = "simple-bus"; > interrupt-parent = <&plic>; > - #address-cells = <1>; > - #size-cells = <1>; > - dma-noncoherent; > - ranges; > - > - uart0: serial@4140000 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x04140000 0x100>; > - interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&osc>; > - reg-shift = <2>; > - reg-io-width = <4>; > - status = "disabled"; > - }; > - > - uart1: serial@4150000 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x04150000 0x100>; > - interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&osc>; > - reg-shift = <2>; > - reg-io-width = <4>; > - status = "disabled"; > - }; > - > - uart2: serial@4160000 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x04160000 0x100>; > - interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&osc>; > - reg-shift = <2>; > - reg-io-width = <4>; > - status = "disabled"; > - }; > - > - uart3: serial@4170000 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x04170000 0x100>; > - interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&osc>; > - reg-shift = <2>; > - reg-io-width = <4>; > - status = "disabled"; > - }; > - > - uart4: serial@41c0000 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x041c0000 0x100>; > - interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&osc>; > - reg-shift = <2>; > - reg-io-width = <4>; > - status = "disabled"; > - }; > > plic: interrupt-controller@70000000 { > compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi > similarity index 80% > copy from arch/riscv/boot/dts/sophgo/cv1800b.dtsi > copy to arch/riscv/boot/dts/sophgo/cv180x.dtsi > index df40e87ee063..ffaf51724c98 100644 > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi > @@ -1,12 +1,12 @@ > // SPDX-License-Identifier: (GPL-2.0 OR MIT) > /* > * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> > */ > > #include <dt-bindings/interrupt-controller/irq.h> > > / { > - compatible = "sophgo,cv1800b"; > #address-cells = <1>; > #size-cells = <1>; > > @@ -48,7 +48,6 @@ osc: oscillator { > > soc { > compatible = "simple-bus"; > - interrupt-parent = <&plic>; > #address-cells = <1>; > #size-cells = <1>; > dma-noncoherent; > @@ -103,21 +102,5 @@ uart4: serial@41c0000 { > reg-io-width = <4>; > status = "disabled"; > }; > - > - plic: interrupt-controller@70000000 { > - compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; > - reg = <0x70000000 0x4000000>; > - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; > - interrupt-controller; > - #address-cells = <0>; > - #interrupt-cells = <2>; > - riscv,ndev = <101>; > - }; > - > - clint: timer@74000000 { > - compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; > - reg = <0x74000000 0x10000>; > - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; > - }; > }; > }; > -- > 2.42.0 >
On 2023/10/9 19:26, Inochi Amaoto wrote: > Move the cpu and the common peripherals of CV181x and CV180x to new file. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > --- > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 95 +------------------ > .../dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} | 19 +--- > 2 files changed, 2 insertions(+), 112 deletions(-) > copy arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} (80%) LGTM Acked-by: Chen Wang <unicorn_wang@outlook.com> > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > index df40e87ee063..0904154f9829 100644 > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > @@ -3,106 +3,13 @@ > * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > */ > > -#include <dt-bindings/interrupt-controller/irq.h> > +#include "cv180x.dtsi" > > / { > compatible = "sophgo,cv1800b"; > - #address-cells = <1>; > - #size-cells = <1>; > - > - cpus: cpus { > - #address-cells = <1>; > - #size-cells = <0>; > - timebase-frequency = <25000000>; > - > - cpu0: cpu@0 { > - compatible = "thead,c906", "riscv"; > - device_type = "cpu"; > - reg = <0>; > - d-cache-block-size = <64>; > - d-cache-sets = <512>; > - d-cache-size = <65536>; > - i-cache-block-size = <64>; > - i-cache-sets = <128>; > - i-cache-size = <32768>; > - mmu-type = "riscv,sv39"; > - riscv,isa = "rv64imafdc"; > - riscv,isa-base = "rv64i"; > - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > - "zifencei", "zihpm"; > - > - cpu0_intc: interrupt-controller { > - compatible = "riscv,cpu-intc"; > - interrupt-controller; > - #address-cells = <0>; > - #interrupt-cells = <1>; > - }; > - }; > - }; > - > - osc: oscillator { > - compatible = "fixed-clock"; > - clock-output-names = "osc_25m"; > - #clock-cells = <0>; > - }; > > soc { > - compatible = "simple-bus"; > interrupt-parent = <&plic>; > - #address-cells = <1>; > - #size-cells = <1>; > - dma-noncoherent; > - ranges; > - > - uart0: serial@4140000 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x04140000 0x100>; > - interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&osc>; > - reg-shift = <2>; > - reg-io-width = <4>; > - status = "disabled"; > - }; > - > - uart1: serial@4150000 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x04150000 0x100>; > - interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&osc>; > - reg-shift = <2>; > - reg-io-width = <4>; > - status = "disabled"; > - }; > - > - uart2: serial@4160000 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x04160000 0x100>; > - interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&osc>; > - reg-shift = <2>; > - reg-io-width = <4>; > - status = "disabled"; > - }; > - > - uart3: serial@4170000 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x04170000 0x100>; > - interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&osc>; > - reg-shift = <2>; > - reg-io-width = <4>; > - status = "disabled"; > - }; > - > - uart4: serial@41c0000 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x041c0000 0x100>; > - interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&osc>; > - reg-shift = <2>; > - reg-io-width = <4>; > - status = "disabled"; > - }; > > plic: interrupt-controller@70000000 { > compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi > similarity index 80% > copy from arch/riscv/boot/dts/sophgo/cv1800b.dtsi > copy to arch/riscv/boot/dts/sophgo/cv180x.dtsi > index df40e87ee063..ffaf51724c98 100644 > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi > @@ -1,12 +1,12 @@ > // SPDX-License-Identifier: (GPL-2.0 OR MIT) > /* > * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> > */ > > #include <dt-bindings/interrupt-controller/irq.h> > > / { > - compatible = "sophgo,cv1800b"; > #address-cells = <1>; > #size-cells = <1>; > > @@ -48,7 +48,6 @@ osc: oscillator { > > soc { > compatible = "simple-bus"; > - interrupt-parent = <&plic>; > #address-cells = <1>; > #size-cells = <1>; > dma-noncoherent; > @@ -103,21 +102,5 @@ uart4: serial@41c0000 { > reg-io-width = <4>; > status = "disabled"; > }; > - > - plic: interrupt-controller@70000000 { > - compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; > - reg = <0x70000000 0x4000000>; > - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; > - interrupt-controller; > - #address-cells = <0>; > - #interrupt-cells = <2>; > - riscv,ndev = <101>; > - }; > - > - clint: timer@74000000 { > - compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; > - reg = <0x74000000 0x10000>; > - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; > - }; > }; > }; > -- > 2.42.0 >
Yo, On Mon, Oct 09, 2023 at 07:26:35PM +0800, Inochi Amaoto wrote: > Move the cpu and the common peripherals of CV181x and CV180x to new file. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > --- > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 95 +------------------ > .../dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} | 19 +--- > 2 files changed, 2 insertions(+), 112 deletions(-) > copy arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} (80%) > > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > index df40e87ee063..0904154f9829 100644 > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > @@ -3,106 +3,13 @@ > * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > */ > > -#include <dt-bindings/interrupt-controller/irq.h> > +#include "cv180x.dtsi" > > / { > compatible = "sophgo,cv1800b"; > - #address-cells = <1>; > - #size-cells = <1>; > - > - cpus: cpus { > - #address-cells = <1>; > - #size-cells = <0>; > - timebase-frequency = <25000000>; > - > - cpu0: cpu@0 { > - compatible = "thead,c906", "riscv"; > - device_type = "cpu"; > - reg = <0>; > - d-cache-block-size = <64>; > - d-cache-sets = <512>; > - d-cache-size = <65536>; > - i-cache-block-size = <64>; > - i-cache-sets = <128>; > - i-cache-size = <32768>; > - mmu-type = "riscv,sv39"; > - riscv,isa = "rv64imafdc"; > - riscv,isa-base = "rv64i"; > - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > - "zifencei", "zihpm"; > - > - cpu0_intc: interrupt-controller { > - compatible = "riscv,cpu-intc"; > - interrupt-controller; > - #address-cells = <0>; > - #interrupt-cells = <1>; > - }; > - }; > - }; > - > - osc: oscillator { > - compatible = "fixed-clock"; > - clock-output-names = "osc_25m"; > - #clock-cells = <0>; > - }; > > soc { > - compatible = "simple-bus"; > interrupt-parent = <&plic>; > - #address-cells = <1>; > - #size-cells = <1>; > - dma-noncoherent; > - ranges; > - > - uart0: serial@4140000 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x04140000 0x100>; > - interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&osc>; > - reg-shift = <2>; > - reg-io-width = <4>; > - status = "disabled"; > - }; > - > - uart1: serial@4150000 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x04150000 0x100>; > - interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&osc>; > - reg-shift = <2>; > - reg-io-width = <4>; > - status = "disabled"; > - }; > - > - uart2: serial@4160000 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x04160000 0x100>; > - interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&osc>; > - reg-shift = <2>; > - reg-io-width = <4>; > - status = "disabled"; > - }; > - > - uart3: serial@4170000 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x04170000 0x100>; > - interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&osc>; > - reg-shift = <2>; > - reg-io-width = <4>; > - status = "disabled"; > - }; > - > - uart4: serial@41c0000 { > - compatible = "snps,dw-apb-uart"; > - reg = <0x041c0000 0x100>; > - interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&osc>; > - reg-shift = <2>; > - reg-io-width = <4>; > - status = "disabled"; > - }; > > plic: interrupt-controller@70000000 { > compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi > similarity index 80% > copy from arch/riscv/boot/dts/sophgo/cv1800b.dtsi > copy to arch/riscv/boot/dts/sophgo/cv180x.dtsi > index df40e87ee063..ffaf51724c98 100644 Firstly, this form of diff really threw me, I was quite confused for a few minutes. A copy plus a pair of diffs doesn't really make much sense, when the operation being carried is an extraction of some nodes to a different file. > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi > @@ -1,12 +1,12 @@ > // SPDX-License-Identifier: (GPL-2.0 OR MIT) > /* > * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> Also, is moving around some bits of hw description really a copyrightable change? > */ > > #include <dt-bindings/interrupt-controller/irq.h> > > / { > - compatible = "sophgo,cv1800b"; > #address-cells = <1>; > #size-cells = <1>; > > @@ -48,7 +48,6 @@ osc: oscillator { > > soc { > compatible = "simple-bus"; > - interrupt-parent = <&plic>; > #address-cells = <1>; > #size-cells = <1>; > dma-noncoherent; > @@ -103,21 +102,5 @@ uart4: serial@41c0000 { > reg-io-width = <4>; > status = "disabled"; > }; > - > - plic: interrupt-controller@70000000 { > - compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; > - reg = <0x70000000 0x4000000>; > - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; > - interrupt-controller; > - #address-cells = <0>; > - #interrupt-cells = <2>; > - riscv,ndev = <101>; > - }; > - > - clint: timer@74000000 { > - compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; > - reg = <0x74000000 0x10000>; > - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; > - }; > }; > }; What I wanted to comment on was this though - it seems that both the cv1800b and the cv1812h have identical plic and clint nodes, other than their compatibles? If that is the case, why create a cv1800b and a cv1812h specific file containing entirely new nodes, when overriding the compatible would be sufficient? Doubly so if the other SoCs in the cv18xx series are going to have identical layouts. I gave it a quick test locally with the below diff applied on top of this series - although I didn't make sure that I didn't re-order the plic & clint nodes, I just wanted to demonstrate what I had done. Cheers, Conor. -- 8< -- diff --git a/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts b/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts index 3af9e34b3bc7..a9d809a49e7a 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts +++ b/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts @@ -5,7 +5,7 @@ /dts-v1/; -#include "cv1800b.dtsi" +#include "cv180x.dtsi" / { model = "Milk-V Duo"; diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi index 0904154f9829..e69de29bb2d1 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> - */ - -#include "cv180x.dtsi" - -/ { - compatible = "sophgo,cv1800b"; - - soc { - interrupt-parent = <&plic>; - - plic: interrupt-controller@70000000 { - compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; - reg = <0x70000000 0x4000000>; - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <2>; - riscv,ndev = <101>; - }; - - clint: timer@74000000 { - compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; - reg = <0x74000000 0x10000>; - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; - }; - }; -}; diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi index 64ffb23d3626..1a2c44ba4de9 100644 --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi @@ -48,6 +48,7 @@ osc: oscillator { soc { compatible = "simple-bus"; + interrupt-parent = <&plic>; #address-cells = <1>; #size-cells = <1>; dma-noncoherent; @@ -174,5 +175,21 @@ uart4: serial@41c0000 { reg-io-width = <4>; status = "disabled"; }; + + plic: interrupt-controller@70000000 { + compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; + reg = <0x70000000 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <101>; + }; + + clint: timer@74000000 { + compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; + reg = <0x74000000 0x10000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; + }; }; }; diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi index 3864d34b0100..c0a8d3290cc8 100644 --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi @@ -15,22 +15,13 @@ memory@80000000 { }; soc { - interrupt-parent = <&plic>; plic: interrupt-controller@70000000 { compatible = "sophgo,cv1812h-plic", "thead,c900-plic"; - reg = <0x70000000 0x4000000>; - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <2>; - riscv,ndev = <101>; }; clint: timer@74000000 { compatible = "sophgo,cv1812h-clint", "thead,c900-clint"; - reg = <0x74000000 0x10000>; - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; }; }; };
>Yo, > >On Mon, Oct 09, 2023 at 07:26:35PM +0800, Inochi Amaoto wrote: >> Move the cpu and the common peripherals of CV181x and CV180x to new file. >> >> Signed-off-by: Inochi Amaoto <inochiama@outlook.com> >> --- >> arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 95 +------------------ >> .../dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} | 19 +--- >> 2 files changed, 2 insertions(+), 112 deletions(-) >> copy arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} (80%) >> >> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi >> index df40e87ee063..0904154f9829 100644 >> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi >> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi >> @@ -3,106 +3,13 @@ >> * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> >> */ >> >> -#include <dt-bindings/interrupt-controller/irq.h> >> +#include "cv180x.dtsi" >> >> / { >> compatible = "sophgo,cv1800b"; >> - #address-cells = <1>; >> - #size-cells = <1>; >> - >> - cpus: cpus { >> - #address-cells = <1>; >> - #size-cells = <0>; >> - timebase-frequency = <25000000>; >> - >> - cpu0: cpu@0 { >> - compatible = "thead,c906", "riscv"; >> - device_type = "cpu"; >> - reg = <0>; >> - d-cache-block-size = <64>; >> - d-cache-sets = <512>; >> - d-cache-size = <65536>; >> - i-cache-block-size = <64>; >> - i-cache-sets = <128>; >> - i-cache-size = <32768>; >> - mmu-type = "riscv,sv39"; >> - riscv,isa = "rv64imafdc"; >> - riscv,isa-base = "rv64i"; >> - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", >> - "zifencei", "zihpm"; >> - >> - cpu0_intc: interrupt-controller { >> - compatible = "riscv,cpu-intc"; >> - interrupt-controller; >> - #address-cells = <0>; >> - #interrupt-cells = <1>; >> - }; >> - }; >> - }; >> - >> - osc: oscillator { >> - compatible = "fixed-clock"; >> - clock-output-names = "osc_25m"; >> - #clock-cells = <0>; >> - }; >> >> soc { >> - compatible = "simple-bus"; >> interrupt-parent = <&plic>; >> - #address-cells = <1>; >> - #size-cells = <1>; >> - dma-noncoherent; >> - ranges; >> - >> - uart0: serial@4140000 { >> - compatible = "snps,dw-apb-uart"; >> - reg = <0x04140000 0x100>; >> - interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; >> - clocks = <&osc>; >> - reg-shift = <2>; >> - reg-io-width = <4>; >> - status = "disabled"; >> - }; >> - >> - uart1: serial@4150000 { >> - compatible = "snps,dw-apb-uart"; >> - reg = <0x04150000 0x100>; >> - interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; >> - clocks = <&osc>; >> - reg-shift = <2>; >> - reg-io-width = <4>; >> - status = "disabled"; >> - }; >> - >> - uart2: serial@4160000 { >> - compatible = "snps,dw-apb-uart"; >> - reg = <0x04160000 0x100>; >> - interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; >> - clocks = <&osc>; >> - reg-shift = <2>; >> - reg-io-width = <4>; >> - status = "disabled"; >> - }; >> - >> - uart3: serial@4170000 { >> - compatible = "snps,dw-apb-uart"; >> - reg = <0x04170000 0x100>; >> - interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; >> - clocks = <&osc>; >> - reg-shift = <2>; >> - reg-io-width = <4>; >> - status = "disabled"; >> - }; >> - >> - uart4: serial@41c0000 { >> - compatible = "snps,dw-apb-uart"; >> - reg = <0x041c0000 0x100>; >> - interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; >> - clocks = <&osc>; >> - reg-shift = <2>; >> - reg-io-width = <4>; >> - status = "disabled"; >> - }; >> >> plic: interrupt-controller@70000000 { >> compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; >> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi >> similarity index 80% >> copy from arch/riscv/boot/dts/sophgo/cv1800b.dtsi >> copy to arch/riscv/boot/dts/sophgo/cv180x.dtsi >> index df40e87ee063..ffaf51724c98 100644 > >Firstly, this form of diff really threw me, I was quite confused for a >few minutes. A copy plus a pair of diffs doesn't really make much sense, >when the operation being carried is an extraction of some nodes to a >different file. > I was told to use -C/-M/-B to generate patch, and the git format-patch give me this wired output if I use -C, using -M seems no change from v1. The -B output is also disappointing. Maybe I need to generate agaion? The v1 version: https://lore.kernel.org/linux-riscv/IA1PR20MB495360B632D106BBB833D82ABBCFA@IA1PR20MB4953.namprd20.prod.outlook.com/ >> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi >> +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi >> @@ -1,12 +1,12 @@ >> // SPDX-License-Identifier: (GPL-2.0 OR MIT) >> /* >> * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> >> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> > >Also, is moving around some bits of hw description really a >copyrightable change? > It seems to be a mistake when I splitting the patch from v1. This copyright should in the next patch. >> */ >> >> #include <dt-bindings/interrupt-controller/irq.h> >> >> / { >> - compatible = "sophgo,cv1800b"; >> #address-cells = <1>; >> #size-cells = <1>; >> >> @@ -48,7 +48,6 @@ osc: oscillator { >> >> soc { >> compatible = "simple-bus"; >> - interrupt-parent = <&plic>; >> #address-cells = <1>; >> #size-cells = <1>; >> dma-noncoherent; >> @@ -103,21 +102,5 @@ uart4: serial@41c0000 { >> reg-io-width = <4>; >> status = "disabled"; >> }; >> - >> - plic: interrupt-controller@70000000 { >> - compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; >> - reg = <0x70000000 0x4000000>; >> - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; >> - interrupt-controller; >> - #address-cells = <0>; >> - #interrupt-cells = <2>; >> - riscv,ndev = <101>; >> - }; >> - >> - clint: timer@74000000 { >> - compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; >> - reg = <0x74000000 0x10000>; >> - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; >> - }; >> }; >> }; > >What I wanted to comment on was this though - it seems that both the >cv1800b and the cv1812h have identical plic and clint nodes, other than >their compatibles? If that is the case, why create a cv1800b and a >cv1812h specific file containing entirely new nodes, when overriding the >compatible would be sufficient? Doubly so if the other SoCs in the >cv18xx series are going to have identical layouts. > >I gave it a quick test locally with the below diff applied on top of >this series - although I didn't make sure that I didn't re-order the >plic & clint nodes, I just wanted to demonstrate what I had done. > Thanks for demonstration. AFAIK, what you said is true. the most devices of CV180x and CV181x are the same, including plic and clint. The reason I used a new one is to identify these two devices without making the compatible string confusing. Should I change the binding name of plic and clint to "sophgo,cv1800-xxx" to mark there are the same series? I think this can avoid this confusing dt nodes. >Cheers, >Conor. >
Sorry for the wrong title. >Yo, > >On Mon, Oct 09, 2023 at 07:26:35PM +0800, Inochi Amaoto wrote: >> Move the cpu and the common peripherals of CV181x and CV180x to new file. >> >> Signed-off-by: Inochi Amaoto <inochiama@outlook.com> >> --- >> arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 95 +------------------ >> .../dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} | 19 +--- >> 2 files changed, 2 insertions(+), 112 deletions(-) >> copy arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} (80%) >> >> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi >> index df40e87ee063..0904154f9829 100644 >> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi >> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi >> @@ -3,106 +3,13 @@ >> * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> >> */ >> >> -#include <dt-bindings/interrupt-controller/irq.h> >> +#include "cv180x.dtsi" >> >> / { >> compatible = "sophgo,cv1800b"; >> - #address-cells = <1>; >> - #size-cells = <1>; >> - >> - cpus: cpus { >> - #address-cells = <1>; >> - #size-cells = <0>; >> - timebase-frequency = <25000000>; >> - >> - cpu0: cpu@0 { >> - compatible = "thead,c906", "riscv"; >> - device_type = "cpu"; >> - reg = <0>; >> - d-cache-block-size = <64>; >> - d-cache-sets = <512>; >> - d-cache-size = <65536>; >> - i-cache-block-size = <64>; >> - i-cache-sets = <128>; >> - i-cache-size = <32768>; >> - mmu-type = "riscv,sv39"; >> - riscv,isa = "rv64imafdc"; >> - riscv,isa-base = "rv64i"; >> - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", >> - "zifencei", "zihpm"; >> - >> - cpu0_intc: interrupt-controller { >> - compatible = "riscv,cpu-intc"; >> - interrupt-controller; >> - #address-cells = <0>; >> - #interrupt-cells = <1>; >> - }; >> - }; >> - }; >> - >> - osc: oscillator { >> - compatible = "fixed-clock"; >> - clock-output-names = "osc_25m"; >> - #clock-cells = <0>; >> - }; >> >> soc { >> - compatible = "simple-bus"; >> interrupt-parent = <&plic>; >> - #address-cells = <1>; >> - #size-cells = <1>; >> - dma-noncoherent; >> - ranges; >> - >> - uart0: serial@4140000 { >> - compatible = "snps,dw-apb-uart"; >> - reg = <0x04140000 0x100>; >> - interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; >> - clocks = <&osc>; >> - reg-shift = <2>; >> - reg-io-width = <4>; >> - status = "disabled"; >> - }; >> - >> - uart1: serial@4150000 { >> - compatible = "snps,dw-apb-uart"; >> - reg = <0x04150000 0x100>; >> - interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; >> - clocks = <&osc>; >> - reg-shift = <2>; >> - reg-io-width = <4>; >> - status = "disabled"; >> - }; >> - >> - uart2: serial@4160000 { >> - compatible = "snps,dw-apb-uart"; >> - reg = <0x04160000 0x100>; >> - interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; >> - clocks = <&osc>; >> - reg-shift = <2>; >> - reg-io-width = <4>; >> - status = "disabled"; >> - }; >> - >> - uart3: serial@4170000 { >> - compatible = "snps,dw-apb-uart"; >> - reg = <0x04170000 0x100>; >> - interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; >> - clocks = <&osc>; >> - reg-shift = <2>; >> - reg-io-width = <4>; >> - status = "disabled"; >> - }; >> - >> - uart4: serial@41c0000 { >> - compatible = "snps,dw-apb-uart"; >> - reg = <0x041c0000 0x100>; >> - interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; >> - clocks = <&osc>; >> - reg-shift = <2>; >> - reg-io-width = <4>; >> - status = "disabled"; >> - }; >> >> plic: interrupt-controller@70000000 { >> compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; >> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi >> similarity index 80% >> copy from arch/riscv/boot/dts/sophgo/cv1800b.dtsi >> copy to arch/riscv/boot/dts/sophgo/cv180x.dtsi >> index df40e87ee063..ffaf51724c98 100644 > >Firstly, this form of diff really threw me, I was quite confused for a >few minutes. A copy plus a pair of diffs doesn't really make much sense, >when the operation being carried is an extraction of some nodes to a >different file. > I was told to use -C/-M/-B to generate patch, and the git format-patch give me this wired output if I use -C, using -M seems no change from v1. The -B output is also disappointing. Maybe I need to generate agaion? The v1 version: https://lore.kernel.org/linux-riscv/IA1PR20MB495360B632D106BBB833D82ABBCFA@IA1PR20MB4953.namprd20.prod.outlook.com/ >> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi >> +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi >> @@ -1,12 +1,12 @@ >> // SPDX-License-Identifier: (GPL-2.0 OR MIT) >> /* >> * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> >> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> > >Also, is moving around some bits of hw description really a >copyrightable change? > It seems to be a mistake when I splitting the patch from v1. This copyright should in the next patch. >> */ >> >> #include <dt-bindings/interrupt-controller/irq.h> >> >> / { >> - compatible = "sophgo,cv1800b"; >> #address-cells = <1>; >> #size-cells = <1>; >> >> @@ -48,7 +48,6 @@ osc: oscillator { >> >> soc { >> compatible = "simple-bus"; >> - interrupt-parent = <&plic>; >> #address-cells = <1>; >> #size-cells = <1>; >> dma-noncoherent; >> @@ -103,21 +102,5 @@ uart4: serial@41c0000 { >> reg-io-width = <4>; >> status = "disabled"; >> }; >> - >> - plic: interrupt-controller@70000000 { >> - compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; >> - reg = <0x70000000 0x4000000>; >> - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; >> - interrupt-controller; >> - #address-cells = <0>; >> - #interrupt-cells = <2>; >> - riscv,ndev = <101>; >> - }; >> - >> - clint: timer@74000000 { >> - compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; >> - reg = <0x74000000 0x10000>; >> - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; >> - }; >> }; >> }; > >What I wanted to comment on was this though - it seems that both the >cv1800b and the cv1812h have identical plic and clint nodes, other than >their compatibles? If that is the case, why create a cv1800b and a >cv1812h specific file containing entirely new nodes, when overriding the >compatible would be sufficient? Doubly so if the other SoCs in the >cv18xx series are going to have identical layouts. > >I gave it a quick test locally with the below diff applied on top of >this series - although I didn't make sure that I didn't re-order the >plic & clint nodes, I just wanted to demonstrate what I had done. > Thanks for demonstration. AFAIK, what you said is true. the most devices of CV180x and CV181x are the same, including plic and clint. The reason I used a new one is to identify these two devices without making the compatible string confusing. Should I change the binding name of plic and clint to "sophgo,cv1800-xxx" to mark there are the same series? I think this can avoid this confusing dt nodes. >Cheers, >Conor. >
On Fri, Oct 13, 2023 at 05:52:03PM +0800, Inochi Amaoto wrote: > Sorry for the wrong title. > > >Yo, > > > >On Mon, Oct 09, 2023 at 07:26:35PM +0800, Inochi Amaoto wrote: > >> Move the cpu and the common peripherals of CV181x and CV180x to new file. > >> > >> Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > >> --- > >> arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 95 +------------------ > >> .../dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} | 19 +--- > >> 2 files changed, 2 insertions(+), 112 deletions(-) > >> copy arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} (80%) > >> > >> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > >> index df40e87ee063..0904154f9829 100644 > >> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > >> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > >> @@ -3,106 +3,13 @@ > >> * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > >> */ > >> > >> -#include <dt-bindings/interrupt-controller/irq.h> > >> +#include "cv180x.dtsi" > >> > >> / { > >> compatible = "sophgo,cv1800b"; > >> - #address-cells = <1>; > >> - #size-cells = <1>; > >> - > >> - cpus: cpus { > >> - #address-cells = <1>; > >> - #size-cells = <0>; > >> - timebase-frequency = <25000000>; > >> - > >> - cpu0: cpu@0 { > >> - compatible = "thead,c906", "riscv"; > >> - device_type = "cpu"; > >> - reg = <0>; > >> - d-cache-block-size = <64>; > >> - d-cache-sets = <512>; > >> - d-cache-size = <65536>; > >> - i-cache-block-size = <64>; > >> - i-cache-sets = <128>; > >> - i-cache-size = <32768>; > >> - mmu-type = "riscv,sv39"; > >> - riscv,isa = "rv64imafdc"; > >> - riscv,isa-base = "rv64i"; > >> - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > >> - "zifencei", "zihpm"; > >> - > >> - cpu0_intc: interrupt-controller { > >> - compatible = "riscv,cpu-intc"; > >> - interrupt-controller; > >> - #address-cells = <0>; > >> - #interrupt-cells = <1>; > >> - }; > >> - }; > >> - }; > >> - > >> - osc: oscillator { > >> - compatible = "fixed-clock"; > >> - clock-output-names = "osc_25m"; > >> - #clock-cells = <0>; > >> - }; > >> > >> soc { > >> - compatible = "simple-bus"; > >> interrupt-parent = <&plic>; > >> - #address-cells = <1>; > >> - #size-cells = <1>; > >> - dma-noncoherent; > >> - ranges; > >> - > >> - uart0: serial@4140000 { > >> - compatible = "snps,dw-apb-uart"; > >> - reg = <0x04140000 0x100>; > >> - interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; > >> - clocks = <&osc>; > >> - reg-shift = <2>; > >> - reg-io-width = <4>; > >> - status = "disabled"; > >> - }; > >> - > >> - uart1: serial@4150000 { > >> - compatible = "snps,dw-apb-uart"; > >> - reg = <0x04150000 0x100>; > >> - interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; > >> - clocks = <&osc>; > >> - reg-shift = <2>; > >> - reg-io-width = <4>; > >> - status = "disabled"; > >> - }; > >> - > >> - uart2: serial@4160000 { > >> - compatible = "snps,dw-apb-uart"; > >> - reg = <0x04160000 0x100>; > >> - interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; > >> - clocks = <&osc>; > >> - reg-shift = <2>; > >> - reg-io-width = <4>; > >> - status = "disabled"; > >> - }; > >> - > >> - uart3: serial@4170000 { > >> - compatible = "snps,dw-apb-uart"; > >> - reg = <0x04170000 0x100>; > >> - interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; > >> - clocks = <&osc>; > >> - reg-shift = <2>; > >> - reg-io-width = <4>; > >> - status = "disabled"; > >> - }; > >> - > >> - uart4: serial@41c0000 { > >> - compatible = "snps,dw-apb-uart"; > >> - reg = <0x041c0000 0x100>; > >> - interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; > >> - clocks = <&osc>; > >> - reg-shift = <2>; > >> - reg-io-width = <4>; > >> - status = "disabled"; > >> - }; > >> > >> plic: interrupt-controller@70000000 { > >> compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; > >> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi > >> similarity index 80% > >> copy from arch/riscv/boot/dts/sophgo/cv1800b.dtsi > >> copy to arch/riscv/boot/dts/sophgo/cv180x.dtsi > >> index df40e87ee063..ffaf51724c98 100644 > > > >Firstly, this form of diff really threw me, I was quite confused for a > >few minutes. A copy plus a pair of diffs doesn't really make much sense, > >when the operation being carried is an extraction of some nodes to a > >different file. > > > > I was told to use -C/-M/-B to generate patch, and the git format-patch > give me this wired output if I use -C, using -M seems no change from v1. > The -B output is also disappointing. Maybe I need to generate agaion? I don't think generating it again is going to change the outcome & I don't really think the -C version of this patch makes much sense, it is hard to tell what has actually been moved. > The v1 version: > https://lore.kernel.org/linux-riscv/IA1PR20MB495360B632D106BBB833D82ABBCFA@IA1PR20MB4953.namprd20.prod.outlook.com/ > > >> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > >> +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi > >> @@ -1,12 +1,12 @@ > >> // SPDX-License-Identifier: (GPL-2.0 OR MIT) > >> /* > >> * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > >> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> > > > >Also, is moving around some bits of hw description really a > >copyrightable change? > > > > It seems to be a mistake when I splitting the patch from v1. > This copyright should in the next patch. > > >> */ > >> > >> #include <dt-bindings/interrupt-controller/irq.h> > >> > >> / { > >> - compatible = "sophgo,cv1800b"; > >> #address-cells = <1>; > >> #size-cells = <1>; > >> > >> @@ -48,7 +48,6 @@ osc: oscillator { > >> > >> soc { > >> compatible = "simple-bus"; > >> - interrupt-parent = <&plic>; > >> #address-cells = <1>; > >> #size-cells = <1>; > >> dma-noncoherent; > >> @@ -103,21 +102,5 @@ uart4: serial@41c0000 { > >> reg-io-width = <4>; > >> status = "disabled"; > >> }; > >> - > >> - plic: interrupt-controller@70000000 { > >> - compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; > >> - reg = <0x70000000 0x4000000>; > >> - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; > >> - interrupt-controller; > >> - #address-cells = <0>; > >> - #interrupt-cells = <2>; > >> - riscv,ndev = <101>; > >> - }; > >> - > >> - clint: timer@74000000 { > >> - compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; > >> - reg = <0x74000000 0x10000>; > >> - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; > >> - }; > >> }; > >> }; > > > >What I wanted to comment on was this though - it seems that both the > >cv1800b and the cv1812h have identical plic and clint nodes, other than > >their compatibles? If that is the case, why create a cv1800b and a > >cv1812h specific file containing entirely new nodes, when overriding the > >compatible would be sufficient? Doubly so if the other SoCs in the > >cv18xx series are going to have identical layouts. > > > >I gave it a quick test locally with the below diff applied on top of > >this series - although I didn't make sure that I didn't re-order the > >plic & clint nodes, I just wanted to demonstrate what I had done. > > > > Thanks for demonstration. AFAIK, what you said is true. the most devices > of CV180x and CV181x are the same, including plic and clint. The reason I > used a new one is to identify these two devices without making the > compatible string confusing. > Should I change the binding name of plic and clint to "sophgo,cv1800-xxx" > to mark there are the same series? I think this can avoid this confusing > dt nodes. I personally don't find the compatibles (or the dt nodes) confusing, so I dunno. Having reusing the compatible is not something that I am a fan of either, since this seems to be a different soc (given the sram & coprocessor etc) even if the addresses of the peripherals are identical.
> >On Fri, Oct 13, 2023 at 05:52:03PM +0800, Inochi Amaoto wrote: >> Sorry for the wrong title. >> >>> Yo, >>> >>> On Mon, Oct 09, 2023 at 07:26:35PM +0800, Inochi Amaoto wrote: >>>> Move the cpu and the common peripherals of CV181x and CV180x to new file. >>>> >>>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com> >>>> --- >>>> arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 95 +------------------ >>>> .../dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} | 19 +--- >>>> 2 files changed, 2 insertions(+), 112 deletions(-) >>>> copy arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} (80%) >>>> >>>> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi >>>> index df40e87ee063..0904154f9829 100644 >>>> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi >>>> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi >>>> @@ -3,106 +3,13 @@ >>>> * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> >>>> */ >>>> >>>> -#include <dt-bindings/interrupt-controller/irq.h> >>>> +#include "cv180x.dtsi" >>>> >>>> / { >>>> compatible = "sophgo,cv1800b"; >>>> - #address-cells = <1>; >>>> - #size-cells = <1>; >>>> - >>>> - cpus: cpus { >>>> - #address-cells = <1>; >>>> - #size-cells = <0>; >>>> - timebase-frequency = <25000000>; >>>> - >>>> - cpu0: cpu@0 { >>>> - compatible = "thead,c906", "riscv"; >>>> - device_type = "cpu"; >>>> - reg = <0>; >>>> - d-cache-block-size = <64>; >>>> - d-cache-sets = <512>; >>>> - d-cache-size = <65536>; >>>> - i-cache-block-size = <64>; >>>> - i-cache-sets = <128>; >>>> - i-cache-size = <32768>; >>>> - mmu-type = "riscv,sv39"; >>>> - riscv,isa = "rv64imafdc"; >>>> - riscv,isa-base = "rv64i"; >>>> - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", >>>> - "zifencei", "zihpm"; >>>> - >>>> - cpu0_intc: interrupt-controller { >>>> - compatible = "riscv,cpu-intc"; >>>> - interrupt-controller; >>>> - #address-cells = <0>; >>>> - #interrupt-cells = <1>; >>>> - }; >>>> - }; >>>> - }; >>>> - >>>> - osc: oscillator { >>>> - compatible = "fixed-clock"; >>>> - clock-output-names = "osc_25m"; >>>> - #clock-cells = <0>; >>>> - }; >>>> >>>> soc { >>>> - compatible = "simple-bus"; >>>> interrupt-parent = <&plic>; >>>> - #address-cells = <1>; >>>> - #size-cells = <1>; >>>> - dma-noncoherent; >>>> - ranges; >>>> - >>>> - uart0: serial@4140000 { >>>> - compatible = "snps,dw-apb-uart"; >>>> - reg = <0x04140000 0x100>; >>>> - interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; >>>> - clocks = <&osc>; >>>> - reg-shift = <2>; >>>> - reg-io-width = <4>; >>>> - status = "disabled"; >>>> - }; >>>> - >>>> - uart1: serial@4150000 { >>>> - compatible = "snps,dw-apb-uart"; >>>> - reg = <0x04150000 0x100>; >>>> - interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; >>>> - clocks = <&osc>; >>>> - reg-shift = <2>; >>>> - reg-io-width = <4>; >>>> - status = "disabled"; >>>> - }; >>>> - >>>> - uart2: serial@4160000 { >>>> - compatible = "snps,dw-apb-uart"; >>>> - reg = <0x04160000 0x100>; >>>> - interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; >>>> - clocks = <&osc>; >>>> - reg-shift = <2>; >>>> - reg-io-width = <4>; >>>> - status = "disabled"; >>>> - }; >>>> - >>>> - uart3: serial@4170000 { >>>> - compatible = "snps,dw-apb-uart"; >>>> - reg = <0x04170000 0x100>; >>>> - interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; >>>> - clocks = <&osc>; >>>> - reg-shift = <2>; >>>> - reg-io-width = <4>; >>>> - status = "disabled"; >>>> - }; >>>> - >>>> - uart4: serial@41c0000 { >>>> - compatible = "snps,dw-apb-uart"; >>>> - reg = <0x041c0000 0x100>; >>>> - interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; >>>> - clocks = <&osc>; >>>> - reg-shift = <2>; >>>> - reg-io-width = <4>; >>>> - status = "disabled"; >>>> - }; >>>> >>>> plic: interrupt-controller@70000000 { >>>> compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; >>>> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi >>>> similarity index 80% >>>> copy from arch/riscv/boot/dts/sophgo/cv1800b.dtsi >>>> copy to arch/riscv/boot/dts/sophgo/cv180x.dtsi >>>> index df40e87ee063..ffaf51724c98 100644 >>> >>> Firstly, this form of diff really threw me, I was quite confused for a >>> few minutes. A copy plus a pair of diffs doesn't really make much sense, >>> when the operation being carried is an extraction of some nodes to a >>> different file. >>> >> >> I was told to use -C/-M/-B to generate patch, and the git format-patch >> give me this wired output if I use -C, using -M seems no change from v1. >> The -B output is also disappointing. Maybe I need to generate agaion? > >I don't think generating it again is going to change the outcome & I >don't really think the -C version of this patch makes much sense, it is >hard to tell what has actually been moved. > I mean regenerating without -C, This shows the the code move, but it gives a huge output, since the git can not detect this move and output all the moved line in the diff as changed. >> The v1 version: >> https://lore.kernel.org/linux-riscv/IA1PR20MB495360B632D106BBB833D82ABBCFA@IA1PR20MB4953.namprd20.prod.outlook.com/ >> >>>> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi >>>> +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi >>>> @@ -1,12 +1,12 @@ >>>> // SPDX-License-Identifier: (GPL-2.0 OR MIT) >>>> /* >>>> * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> >>>> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> >>> >>> Also, is moving around some bits of hw description really a >>> copyrightable change? >>> >> >> It seems to be a mistake when I splitting the patch from v1. >> This copyright should in the next patch. >> >>>> */ >>>> >>>> #include <dt-bindings/interrupt-controller/irq.h> >>>> >>>> / { >>>> - compatible = "sophgo,cv1800b"; >>>> #address-cells = <1>; >>>> #size-cells = <1>; >>>> >>>> @@ -48,7 +48,6 @@ osc: oscillator { >>>> >>>> soc { >>>> compatible = "simple-bus"; >>>> - interrupt-parent = <&plic>; >>>> #address-cells = <1>; >>>> #size-cells = <1>; >>>> dma-noncoherent; >>>> @@ -103,21 +102,5 @@ uart4: serial@41c0000 { >>>> reg-io-width = <4>; >>>> status = "disabled"; >>>> }; >>>> - >>>> - plic: interrupt-controller@70000000 { >>>> - compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; >>>> - reg = <0x70000000 0x4000000>; >>>> - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; >>>> - interrupt-controller; >>>> - #address-cells = <0>; >>>> - #interrupt-cells = <2>; >>>> - riscv,ndev = <101>; >>>> - }; >>>> - >>>> - clint: timer@74000000 { >>>> - compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; >>>> - reg = <0x74000000 0x10000>; >>>> - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; >>>> - }; >>>> }; >>>> }; >>> >>> What I wanted to comment on was this though - it seems that both the >>> cv1800b and the cv1812h have identical plic and clint nodes, other than >>> their compatibles? If that is the case, why create a cv1800b and a >>> cv1812h specific file containing entirely new nodes, when overriding the >>> compatible would be sufficient? Doubly so if the other SoCs in the >>> cv18xx series are going to have identical layouts. >>> >>> I gave it a quick test locally with the below diff applied on top of >>> this series - although I didn't make sure that I didn't re-order the >>> plic & clint nodes, I just wanted to demonstrate what I had done. >>> >> >> Thanks for demonstration. AFAIK, what you said is true. the most devices >> of CV180x and CV181x are the same, including plic and clint. The reason I >> used a new one is to identify these two devices without making the >> compatible string confusing. >> Should I change the binding name of plic and clint to "sophgo,cv1800-xxx" >> to mark there are the same series? I think this can avoid this confusing >> dt nodes. > >I personally don't find the compatibles (or the dt nodes) confusing, so >I dunno. Having reusing the compatible is not something that I am a fan of >either, since this seems to be a different soc (given the sram & >coprocessor etc) even if the addresses of the peripherals are identical. Thanks. It is more like I have misunderstood something. > >
On Fri, Oct 13, 2023 at 10:08:24AM +0100, Conor Dooley wrote: > Yo, > > On Mon, Oct 09, 2023 at 07:26:35PM +0800, Inochi Amaoto wrote: > > Move the cpu and the common peripherals of CV181x and CV180x to new file. > > ... > > }; > > }; > > What I wanted to comment on was this though - it seems that both the > cv1800b and the cv1812h have identical plic and clint nodes, other than > their compatibles? If that is the case, why create a cv1800b and a > cv1812h specific file containing entirely new nodes, when overriding the > compatible would be sufficient? Doubly so if the other SoCs in the > cv18xx series are going to have identical layouts. > > I gave it a quick test locally with the below diff applied on top of > this series - although I didn't make sure that I didn't re-order the > plic & clint nodes, I just wanted to demonstrate what I had done. > > Cheers, > Conor. > > -- 8< -- > > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts b/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts > index 3af9e34b3bc7..a9d809a49e7a 100644 > --- a/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts > +++ b/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts > @@ -5,7 +5,7 @@ > > /dts-v1/; > > -#include "cv1800b.dtsi" > +#include "cv180x.dtsi" > > / { > model = "Milk-V Duo"; > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > index 0904154f9829..e69de29bb2d1 100644 > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > @@ -1,30 +0,0 @@ > -// SPDX-License-Identifier: (GPL-2.0 OR MIT) > -/* > - * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > - */ > - > -#include "cv180x.dtsi" > - > -/ { > - compatible = "sophgo,cv1800b"; > - > - soc { > - interrupt-parent = <&plic>; > - > - plic: interrupt-controller@70000000 { > - compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; > - reg = <0x70000000 0x4000000>; > - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; > - interrupt-controller; > - #address-cells = <0>; > - #interrupt-cells = <2>; > - riscv,ndev = <101>; > - }; > - > - clint: timer@74000000 { > - compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; > - reg = <0x74000000 0x10000>; > - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; > - }; > - }; > -}; > diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi > index 64ffb23d3626..1a2c44ba4de9 100644 > --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi > @@ -48,6 +48,7 @@ osc: oscillator { > > soc { > compatible = "simple-bus"; > + interrupt-parent = <&plic>; > #address-cells = <1>; > #size-cells = <1>; > dma-noncoherent; > @@ -174,5 +175,21 @@ uart4: serial@41c0000 { > reg-io-width = <4>; > status = "disabled"; > }; > + > + plic: interrupt-controller@70000000 { > + compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; > + reg = <0x70000000 0x4000000>; > + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <2>; > + riscv,ndev = <101>; > + }; > + > + clint: timer@74000000 { > + compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; > + reg = <0x74000000 0x10000>; > + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; > + }; > }; > }; > diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi > index 3864d34b0100..c0a8d3290cc8 100644 > --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi > @@ -15,22 +15,13 @@ memory@80000000 { > }; > > soc { > - interrupt-parent = <&plic>; > > plic: interrupt-controller@70000000 { > compatible = "sophgo,cv1812h-plic", "thead,c900-plic"; Hi Conor, Maybe this has been discussed before but I didn't find it. I'm wondering the reason of adding each plic and clint binding for each SoC, can we just use the thead,c900-plic for plic? FWICT, arm gic dt usage follows this way, there's no binding for each SoC's gic but directly use "arm,gic-v3" and so on. Thanks in advance > - reg = <0x70000000 0x4000000>; > - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; > - interrupt-controller; > - #address-cells = <0>; > - #interrupt-cells = <2>; > - riscv,ndev = <101>; > }; > > clint: timer@74000000 { > compatible = "sophgo,cv1812h-clint", "thead,c900-clint"; > - reg = <0x74000000 0x10000>; > - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> Maybe this has been discussed before but I didn't find it. I'm wondering > the reason of adding each plic and clint binding for each SoC, can we > just use the thead,c900-plic for plic? > FWICT, arm gic dt usage follows this way, there's no binding for each SoC's > gic but directly use "arm,gic-v3" and so on. I'm not aware of why the gic-v3 is done like this, but having different compatibles allows differentiation between implementations/integrations of this interrupt controller. I think having that ability is especially helpful given T-Head have open-sourced a bunch of their IP.
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi index df40e87ee063..0904154f9829 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -3,106 +3,13 @@ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> */ -#include <dt-bindings/interrupt-controller/irq.h> +#include "cv180x.dtsi" / { compatible = "sophgo,cv1800b"; - #address-cells = <1>; - #size-cells = <1>; - - cpus: cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <25000000>; - - cpu0: cpu@0 { - compatible = "thead,c906", "riscv"; - device_type = "cpu"; - reg = <0>; - d-cache-block-size = <64>; - d-cache-sets = <512>; - d-cache-size = <65536>; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <32768>; - mmu-type = "riscv,sv39"; - riscv,isa = "rv64imafdc"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; - - cpu0_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - }; - - osc: oscillator { - compatible = "fixed-clock"; - clock-output-names = "osc_25m"; - #clock-cells = <0>; - }; soc { - compatible = "simple-bus"; interrupt-parent = <&plic>; - #address-cells = <1>; - #size-cells = <1>; - dma-noncoherent; - ranges; - - uart0: serial@4140000 { - compatible = "snps,dw-apb-uart"; - reg = <0x04140000 0x100>; - interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: serial@4150000 { - compatible = "snps,dw-apb-uart"; - reg = <0x04150000 0x100>; - interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@4160000 { - compatible = "snps,dw-apb-uart"; - reg = <0x04160000 0x100>; - interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart3: serial@4170000 { - compatible = "snps,dw-apb-uart"; - reg = <0x04170000 0x100>; - interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart4: serial@41c0000 { - compatible = "snps,dw-apb-uart"; - reg = <0x041c0000 0x100>; - interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; plic: interrupt-controller@70000000 { compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi similarity index 80% copy from arch/riscv/boot/dts/sophgo/cv1800b.dtsi copy to arch/riscv/boot/dts/sophgo/cv180x.dtsi index df40e87ee063..ffaf51724c98 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi @@ -1,12 +1,12 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> */ #include <dt-bindings/interrupt-controller/irq.h> / { - compatible = "sophgo,cv1800b"; #address-cells = <1>; #size-cells = <1>; @@ -48,7 +48,6 @@ osc: oscillator { soc { compatible = "simple-bus"; - interrupt-parent = <&plic>; #address-cells = <1>; #size-cells = <1>; dma-noncoherent; @@ -103,21 +102,5 @@ uart4: serial@41c0000 { reg-io-width = <4>; status = "disabled"; }; - - plic: interrupt-controller@70000000 { - compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; - reg = <0x70000000 0x4000000>; - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <2>; - riscv,ndev = <101>; - }; - - clint: timer@74000000 { - compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; - reg = <0x74000000 0x10000>; - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; - }; }; };
Move the cpu and the common peripherals of CV181x and CV180x to new file. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 95 +------------------ .../dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} | 19 +--- 2 files changed, 2 insertions(+), 112 deletions(-) copy arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv180x.dtsi} (80%) -- 2.42.0