| Message ID | 20231012083729.2148044-1-mripard@kernel.org (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Headers | show |
| Series | clk: socfpga: gate: Account for the divider in determine_rate | expand |
Quoting Maxime Ripard (2023-10-12 01:37:29) > Commit 9607beb917df ("clk: socfpga: gate: Add a determine_rate hook") > added a determine_rate implementation set to the > clk_hw_determine_rate_no_reparent, but failed to account for the > internal divider that wasn't used before anywhere but in recalc_rate. > > This led to inconsistencies between the clock rate stored in > clk_core->rate and the one returned by clk_round_rate() that leverages > determine_rate(). > > Since that driver seems to be widely used (and thus regression-prone) > and not supporting rate changes (since it's missing a .set_rate > implementation), we can just report the current divider programmed in > the clock but not try to change it in any way. > > This should be good enough to fix the issues reported, and if someone > ever wants to allow the divider to change then it should be easy enough > using the clk-divider helpers. > > Link: https://lore.kernel.org/linux-clk/20231005095927.12398-2-b.spranger@linutronix.de/ > Fixes: 9607beb917df ("clk: socfpga: gate: Add a determine_rate hook") > Reported-by: Benedikt Spranger <b.spranger@linutronix.de> > Signed-off-by: Maxime Ripard <mripard@kernel.org> > --- Applied to clk-fixes
Am Thu, 12 Oct 2023 10:37:29 +0200 schrieb Maxime Ripard <mripard@kernel.org>: > Commit 9607beb917df ("clk: socfpga: gate: Add a determine_rate hook") > added a determine_rate implementation set to the > clk_hw_determine_rate_no_reparent, but failed to account for the > internal divider that wasn't used before anywhere but in recalc_rate. > > This led to inconsistencies between the clock rate stored in > clk_core->rate and the one returned by clk_round_rate() that leverages > determine_rate(). > > Since that driver seems to be widely used (and thus regression-prone) > and not supporting rate changes (since it's missing a .set_rate > implementation), we can just report the current divider programmed in > the clock but not try to change it in any way. > > This should be good enough to fix the issues reported, and if someone > ever wants to allow the divider to change then it should be easy enough > using the clk-divider helpers. > > Link: https://lore.kernel.org/linux-clk/20231005095927.12398-2-b.spranger@linutronix.de/ > Fixes: 9607beb917df ("clk: socfpga: gate: Add a determine_rate hook") > Reported-by: Benedikt Spranger <b.spranger@linutronix.de> > Signed-off-by: Maxime Ripard <mripard@kernel.org> To compile the patch I need that minor fix: diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c index 486a4d84e418..0a5a95e0267f 100644 --- a/drivers/clk/socfpga/clk-gate.c +++ b/drivers/clk/socfpga/clk-gate.c @@ -116,7 +116,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk, } -static int socfpga_clk_determine_rate(struct clk_hw *hw, +static int socfpga_clk_determine_rate(struct clk_hw *hwclk, struct clk_rate_request *req) { struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); Thanks for the fix and your work. Tested-by: Benedikt Spranger <b.spranger@linutronix.de>
diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c index 8dd601bd8538..486a4d84e418 100644 --- a/drivers/clk/socfpga/clk-gate.c +++ b/drivers/clk/socfpga/clk-gate.c @@ -87,10 +87,8 @@ static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent) return 0; } -static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk, - unsigned long parent_rate) +static u32 socfpga_clk_get_div(struct socfpga_gate_clk *socfpgaclk) { - struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); u32 div = 1, val; if (socfpgaclk->fixed_div) @@ -105,12 +103,33 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk, div = (1 << val); } + return div; +} + +static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk, + unsigned long parent_rate) +{ + struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); + u32 div = socfpga_clk_get_div(socfpgaclk); + return parent_rate / div; } + +static int socfpga_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); + u32 div = socfpga_clk_get_div(socfpgaclk); + + req->rate = req->best_parent_rate / div; + + return 0; +} + static struct clk_ops gateclk_ops = { .recalc_rate = socfpga_clk_recalc_rate, - .determine_rate = clk_hw_determine_rate_no_reparent, + .determine_rate = socfpga_clk_determine_rate, .get_parent = socfpga_clk_get_parent, .set_parent = socfpga_clk_set_parent, };
Commit 9607beb917df ("clk: socfpga: gate: Add a determine_rate hook") added a determine_rate implementation set to the clk_hw_determine_rate_no_reparent, but failed to account for the internal divider that wasn't used before anywhere but in recalc_rate. This led to inconsistencies between the clock rate stored in clk_core->rate and the one returned by clk_round_rate() that leverages determine_rate(). Since that driver seems to be widely used (and thus regression-prone) and not supporting rate changes (since it's missing a .set_rate implementation), we can just report the current divider programmed in the clock but not try to change it in any way. This should be good enough to fix the issues reported, and if someone ever wants to allow the divider to change then it should be easy enough using the clk-divider helpers. Link: https://lore.kernel.org/linux-clk/20231005095927.12398-2-b.spranger@linutronix.de/ Fixes: 9607beb917df ("clk: socfpga: gate: Add a determine_rate hook") Reported-by: Benedikt Spranger <b.spranger@linutronix.de> Signed-off-by: Maxime Ripard <mripard@kernel.org> --- drivers/clk/socfpga/clk-gate.c | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-)