| Message ID | cover.1697200833.git.geert+renesas@glider.be (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | [GIT,PULL] clk: renesas: Updates for v6.7 (take two) | expand |
Quoting Geert Uytterhoeven (2023-10-13 05:48:24) > Hi Mike, Stephen, > > > The following changes since commit 87882525e5ddae7ef6f1b1df5e1eda9bcbcd7720: > > clk: renesas: r8a7795: Constify r8a7795_*_clks (2023-09-26 09:38:00 +0200) > > are available in the Git repository at: > > git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git tags/renesas-clk-for-v6.7-tag2 > > for you to fetch changes up to 4bce4bedbe6daa54cf701184601f913a0c00bb1c: > > clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2 (2023-10-12 20:05:52 +0200) > > ---------------------------------------------------------------- Thanks. Pulled into clk-next
Hi Mike, Stephen, The following changes since commit 87882525e5ddae7ef6f1b1df5e1eda9bcbcd7720: clk: renesas: r8a7795: Constify r8a7795_*_clks (2023-09-26 09:38:00 +0200) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git tags/renesas-clk-for-v6.7-tag2 for you to fetch changes up to 4bce4bedbe6daa54cf701184601f913a0c00bb1c: clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2 (2023-10-12 20:05:52 +0200) ---------------------------------------------------------------- clk: renesas: Updates for v6.7 (take two) - Add support for the RZ/G3S (R9A08G045) SoC, - Miscellaneous fixes and improvements. Note that the clock definitions for the Renesas RZ/G3S (R9A08G045) SoC are shared by clock driver and DT source files, and are part of a PR for SoC, too. Thanks for pulling! ---------------------------------------------------------------- Claudiu Beznea (14): dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3S SoC clk: renesas: rzg2l: Wait for status bit of SD mux before continuing clk: renesas: rzg2l: Lock around writes to mux register clk: renesas: rzg2l: Trust value returned by hardware clk: renesas: rzg2l: Fix computation formula clk: renesas: rzg2l: Remove critical area clk: renesas: rzg2l: Add support for RZ/G3S PLL clk: renesas: rzg2l: Add struct clk_hw_data clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header clk: renesas: rzg2l: Refactor SD mux driver clk: renesas: rzg2l: Add divider clock for RZ/G3S clk: renesas: Add minimal boot support for RZ/G3S SoC clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R() clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2 Dirk Behme (1): clk: renesas: rcar-gen3: Extend SDnH divider table Geert Uytterhoeven (1): Merge tag 'renesas-r9a08g045-dt-binding-defs-tag' into renesas-clk-for-v6.7 .../bindings/clock/renesas,rzg2l-cpg.yaml | 1 + drivers/clk/renesas/Kconfig | 7 +- drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r9a07g043-cpg.c | 19 +- drivers/clk/renesas/r9a07g044-cpg.c | 19 +- drivers/clk/renesas/r9a08g045-cpg.c | 248 +++++++++++ drivers/clk/renesas/rcar-cpg-lib.c | 15 +- drivers/clk/renesas/rzg2l-cpg.c | 452 +++++++++++++++++---- drivers/clk/renesas/rzg2l-cpg.h | 35 +- include/dt-bindings/clock/r9a08g045-cpg.h | 242 +++++++++++ 10 files changed, 954 insertions(+), 85 deletions(-) create mode 100644 drivers/clk/renesas/r9a08g045-cpg.c create mode 100644 include/dt-bindings/clock/r9a08g045-cpg.h Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds