| Message ID | 20231016111743.30331-3-miguel.luis@oracle.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64/kvm: Fine grain _EL2 system registers list that affect nested virtualization | expand |
On 10/16/23 13:17, Miguel Luis wrote: > Some _EL2 encodings are missing. Add them. > > Signed-off-by: Miguel Luis <miguel.luis@oracle.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Eric > --- > arch/arm64/include/asm/sysreg.h | 39 +++++++++++++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index ba5db50effec..8653fb67a339 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -270,6 +270,8 @@ > /* ETM */ > #define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4) > > +#define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0) > + > #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) > #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) > #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) > @@ -484,6 +486,7 @@ > > #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0) > #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1) > +#define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3) > #define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0) > #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1) > #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2) > @@ -497,6 +500,10 @@ > #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) > > #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) > +#define SYS_SDER32_EL2 sys_reg(3, 4, 1, 3, 1) > +#define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0) > +#define SYS_VSTTBR_EL2 sys_reg(3, 4, 2, 6, 0) > +#define SYS_VSTCR_EL2 sys_reg(3, 4, 2, 6, 2) > #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) > #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) > #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) > @@ -514,6 +521,18 @@ > > #define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0) > #define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0) > +#define SYS_MPAMHCR_EL2 sys_reg(3, 4, 10, 4, 0) > +#define SYS_MPAMVPMV_EL2 sys_reg(3, 4, 10, 4, 1) > +#define SYS_MPAM2_EL2 sys_reg(3, 4, 10, 5, 0) > +#define __SYS__MPAMVPMx_EL2(x) sys_reg(3, 4, 10, 6, x) > +#define SYS_MPAMVPM0_EL2 __SYS__MPAMVPMx_EL2(0) > +#define SYS_MPAMVPM1_EL2 __SYS__MPAMVPMx_EL2(1) > +#define SYS_MPAMVPM2_EL2 __SYS__MPAMVPMx_EL2(2) > +#define SYS_MPAMVPM3_EL2 __SYS__MPAMVPMx_EL2(3) > +#define SYS_MPAMVPM4_EL2 __SYS__MPAMVPMx_EL2(4) > +#define SYS_MPAMVPM5_EL2 __SYS__MPAMVPMx_EL2(5) > +#define SYS_MPAMVPM6_EL2 __SYS__MPAMVPMx_EL2(6) > +#define SYS_MPAMVPM7_EL2 __SYS__MPAMVPMx_EL2(7) > > #define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0) > #define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1) > @@ -562,9 +581,29 @@ > > #define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1) > #define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2) > +#define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7) > + > +#define __AMEV_op2(m) (m & 0x7) > +#define __AMEV_CRm(n, m) (n | ((m & 0x8) >> 3)) > +#define __SYS__AMEVCNTVOFF0n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m)) > +#define SYS_AMEVCNTVOFF0n_EL2(m) __SYS__AMEVCNTVOFF0n_EL2(m) > +#define __SYS__AMEVCNTVOFF1n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m)) > +#define SYS_AMEVCNTVOFF1n_EL2(m) __SYS__AMEVCNTVOFF1n_EL2(m) > > #define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3) > #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0) > +#define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0) > +#define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1) > +#define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2) > +#define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0) > +#define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1) > +#define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2) > +#define SYS_CNTHVS_TVAL_EL2 sys_reg(3, 4, 14, 4, 0) > +#define SYS_CNTHVS_CTL_EL2 sys_reg(3, 4, 14, 4, 1) > +#define SYS_CNTHVS_CVAL_EL2 sys_reg(3, 4, 14, 4, 2) > +#define SYS_CNTHPS_TVAL_EL2 sys_reg(3, 4, 14, 5, 0) > +#define SYS_CNTHPS_CTL_EL2 sys_reg(3, 4, 14, 5, 1) > +#define SYS_CNTHPS_CVAL_EL2 sys_reg(3, 4, 14, 5, 2) > > /* VHE encodings for architectural EL0/1 system registers */ > #define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
Hi Eric, > On 16 Oct 2023, at 11:31, Eric Auger <eric.auger@redhat.com> wrote: > > > > On 10/16/23 13:17, Miguel Luis wrote: >> Some _EL2 encodings are missing. Add them. >> >> Signed-off-by: Miguel Luis <miguel.luis@oracle.com> > Reviewed-by: Eric Auger <eric.auger@redhat.com> > Thank you! Miguel > Eric >> --- >> arch/arm64/include/asm/sysreg.h | 39 +++++++++++++++++++++++++++++++++ >> 1 file changed, 39 insertions(+) >> >> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h >> index ba5db50effec..8653fb67a339 100644 >> --- a/arch/arm64/include/asm/sysreg.h >> +++ b/arch/arm64/include/asm/sysreg.h >> @@ -270,6 +270,8 @@ >> /* ETM */ >> #define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4) >> >> +#define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0) >> + >> #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) >> #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) >> #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) >> @@ -484,6 +486,7 @@ >> >> #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0) >> #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1) >> +#define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3) >> #define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0) >> #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1) >> #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2) >> @@ -497,6 +500,10 @@ >> #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) >> >> #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) >> +#define SYS_SDER32_EL2 sys_reg(3, 4, 1, 3, 1) >> +#define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0) >> +#define SYS_VSTTBR_EL2 sys_reg(3, 4, 2, 6, 0) >> +#define SYS_VSTCR_EL2 sys_reg(3, 4, 2, 6, 2) >> #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) >> #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) >> #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) >> @@ -514,6 +521,18 @@ >> >> #define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0) >> #define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0) >> +#define SYS_MPAMHCR_EL2 sys_reg(3, 4, 10, 4, 0) >> +#define SYS_MPAMVPMV_EL2 sys_reg(3, 4, 10, 4, 1) >> +#define SYS_MPAM2_EL2 sys_reg(3, 4, 10, 5, 0) >> +#define __SYS__MPAMVPMx_EL2(x) sys_reg(3, 4, 10, 6, x) >> +#define SYS_MPAMVPM0_EL2 __SYS__MPAMVPMx_EL2(0) >> +#define SYS_MPAMVPM1_EL2 __SYS__MPAMVPMx_EL2(1) >> +#define SYS_MPAMVPM2_EL2 __SYS__MPAMVPMx_EL2(2) >> +#define SYS_MPAMVPM3_EL2 __SYS__MPAMVPMx_EL2(3) >> +#define SYS_MPAMVPM4_EL2 __SYS__MPAMVPMx_EL2(4) >> +#define SYS_MPAMVPM5_EL2 __SYS__MPAMVPMx_EL2(5) >> +#define SYS_MPAMVPM6_EL2 __SYS__MPAMVPMx_EL2(6) >> +#define SYS_MPAMVPM7_EL2 __SYS__MPAMVPMx_EL2(7) >> >> #define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0) >> #define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1) >> @@ -562,9 +581,29 @@ >> >> #define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1) >> #define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2) >> +#define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7) >> + >> +#define __AMEV_op2(m) (m & 0x7) >> +#define __AMEV_CRm(n, m) (n | ((m & 0x8) >> 3)) >> +#define __SYS__AMEVCNTVOFF0n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m)) >> +#define SYS_AMEVCNTVOFF0n_EL2(m) __SYS__AMEVCNTVOFF0n_EL2(m) >> +#define __SYS__AMEVCNTVOFF1n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m)) >> +#define SYS_AMEVCNTVOFF1n_EL2(m) __SYS__AMEVCNTVOFF1n_EL2(m) >> >> #define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3) >> #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0) >> +#define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0) >> +#define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1) >> +#define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2) >> +#define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0) >> +#define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1) >> +#define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2) >> +#define SYS_CNTHVS_TVAL_EL2 sys_reg(3, 4, 14, 4, 0) >> +#define SYS_CNTHVS_CTL_EL2 sys_reg(3, 4, 14, 4, 1) >> +#define SYS_CNTHVS_CVAL_EL2 sys_reg(3, 4, 14, 4, 2) >> +#define SYS_CNTHPS_TVAL_EL2 sys_reg(3, 4, 14, 5, 0) >> +#define SYS_CNTHPS_CTL_EL2 sys_reg(3, 4, 14, 5, 1) >> +#define SYS_CNTHPS_CVAL_EL2 sys_reg(3, 4, 14, 5, 2) >> >> /* VHE encodings for architectural EL0/1 system registers */ >> #define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0) >
On Mon, 16 Oct 2023 12:17:41 +0100, Miguel Luis <miguel.luis@oracle.com> wrote: > > Some _EL2 encodings are missing. Add them. > > Signed-off-by: Miguel Luis <miguel.luis@oracle.com> > --- > arch/arm64/include/asm/sysreg.h | 39 +++++++++++++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index ba5db50effec..8653fb67a339 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h [...] > +#define SYS_SDER32_EL2 sys_reg(3, 4, 1, 3, 1) [...] > +#define SYS_VSTTBR_EL2 sys_reg(3, 4, 2, 6, 0) > +#define SYS_VSTCR_EL2 sys_reg(3, 4, 2, 6, 2) [...] > +#define SYS_CNTHVS_TVAL_EL2 sys_reg(3, 4, 14, 4, 0) > +#define SYS_CNTHVS_CTL_EL2 sys_reg(3, 4, 14, 4, 1) > +#define SYS_CNTHVS_CVAL_EL2 sys_reg(3, 4, 14, 4, 2) > +#define SYS_CNTHPS_TVAL_EL2 sys_reg(3, 4, 14, 5, 0) > +#define SYS_CNTHPS_CTL_EL2 sys_reg(3, 4, 14, 5, 1) > +#define SYS_CNTHPS_CVAL_EL2 sys_reg(3, 4, 14, 5, 2) While the secure definitions seem correct, what is the rationale behind their presence here? They cannot be trapped from non-secure, and the pseudocode is pretty explicit: if !IsCurrentSecurityState(SS_Secure) then UNDEFINED; Given that, they cannot be trapped, handled or accessed from a KVM guest, as Linux on arm64 *always* runs non-secure. M.
Hi Marc, > On 19 Oct 2023, at 11:39, Marc Zyngier <maz@kernel.org> wrote: > > On Mon, 16 Oct 2023 12:17:41 +0100, > Miguel Luis <miguel.luis@oracle.com> wrote: >> >> Some _EL2 encodings are missing. Add them. >> >> Signed-off-by: Miguel Luis <miguel.luis@oracle.com> >> --- >> arch/arm64/include/asm/sysreg.h | 39 +++++++++++++++++++++++++++++++++ >> 1 file changed, 39 insertions(+) >> >> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h >> index ba5db50effec..8653fb67a339 100644 >> --- a/arch/arm64/include/asm/sysreg.h >> +++ b/arch/arm64/include/asm/sysreg.h > > [...] > >> +#define SYS_SDER32_EL2 sys_reg(3, 4, 1, 3, 1) > > [...] > >> +#define SYS_VSTTBR_EL2 sys_reg(3, 4, 2, 6, 0) >> +#define SYS_VSTCR_EL2 sys_reg(3, 4, 2, 6, 2) > > [...] > >> +#define SYS_CNTHVS_TVAL_EL2 sys_reg(3, 4, 14, 4, 0) >> +#define SYS_CNTHVS_CTL_EL2 sys_reg(3, 4, 14, 4, 1) >> +#define SYS_CNTHVS_CVAL_EL2 sys_reg(3, 4, 14, 4, 2) >> +#define SYS_CNTHPS_TVAL_EL2 sys_reg(3, 4, 14, 5, 0) >> +#define SYS_CNTHPS_CTL_EL2 sys_reg(3, 4, 14, 5, 1) >> +#define SYS_CNTHPS_CVAL_EL2 sys_reg(3, 4, 14, 5, 2) > > While the secure definitions seem correct, what is the rationale > behind their presence here? They cannot be trapped from non-secure, > and the pseudocode is pretty explicit: > > if !IsCurrentSecurityState(SS_Secure) then > UNDEFINED; > > Given that, they cannot be trapped, handled or accessed from a KVM > guest, as Linux on arm64 *always* runs non-secure. > Thank you for clarifying. Those definitions were needed for the refinement on patch 3 which clearly didn’t considered that statement beforehand. Yet, should we keep them here so they could be used? Thank you Miguel > M. > > -- > Without deviation from the norm, progress is not possible.
On Thu, 19 Oct 2023 14:23:09 +0100, Miguel Luis <miguel.luis@oracle.com> wrote: > > Hi Marc, > > > On 19 Oct 2023, at 11:39, Marc Zyngier <maz@kernel.org> wrote: > > > > On Mon, 16 Oct 2023 12:17:41 +0100, > > Miguel Luis <miguel.luis@oracle.com> wrote: > >> > >> Some _EL2 encodings are missing. Add them. > >> > >> Signed-off-by: Miguel Luis <miguel.luis@oracle.com> > >> --- > >> arch/arm64/include/asm/sysreg.h | 39 +++++++++++++++++++++++++++++++++ > >> 1 file changed, 39 insertions(+) > >> > >> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > >> index ba5db50effec..8653fb67a339 100644 > >> --- a/arch/arm64/include/asm/sysreg.h > >> +++ b/arch/arm64/include/asm/sysreg.h > > > > [...] > > > >> +#define SYS_SDER32_EL2 sys_reg(3, 4, 1, 3, 1) > > > > [...] > > > >> +#define SYS_VSTTBR_EL2 sys_reg(3, 4, 2, 6, 0) > >> +#define SYS_VSTCR_EL2 sys_reg(3, 4, 2, 6, 2) > > > > [...] > > > >> +#define SYS_CNTHVS_TVAL_EL2 sys_reg(3, 4, 14, 4, 0) > >> +#define SYS_CNTHVS_CTL_EL2 sys_reg(3, 4, 14, 4, 1) > >> +#define SYS_CNTHVS_CVAL_EL2 sys_reg(3, 4, 14, 4, 2) > >> +#define SYS_CNTHPS_TVAL_EL2 sys_reg(3, 4, 14, 5, 0) > >> +#define SYS_CNTHPS_CTL_EL2 sys_reg(3, 4, 14, 5, 1) > >> +#define SYS_CNTHPS_CVAL_EL2 sys_reg(3, 4, 14, 5, 2) > > > > While the secure definitions seem correct, what is the rationale > > behind their presence here? They cannot be trapped from non-secure, > > and the pseudocode is pretty explicit: > > > > if !IsCurrentSecurityState(SS_Secure) then > > UNDEFINED; > > > > Given that, they cannot be trapped, handled or accessed from a KVM > > guest, as Linux on arm64 *always* runs non-secure. > > > > Thank you for clarifying. > > Those definitions were needed for the refinement on patch 3 which clearly > didn’t considered that statement beforehand. > > Yet, should we keep them here so they could be used? But that's the whole point: they *cannot* be used. You can't use a secure system register in non-secure, and we *always* run in non-secure, no ifs no buts. If a guest ever uses one of those, it will get an UNDEF exception directly, without any SW intervention, because that's just illegal. KVM will never see it. As far as Linux is concerned, this is purely dead code. M.
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index ba5db50effec..8653fb67a339 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -270,6 +270,8 @@ /* ETM */ #define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4) +#define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0) + #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) @@ -484,6 +486,7 @@ #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0) #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1) +#define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3) #define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0) #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1) #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2) @@ -497,6 +500,10 @@ #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) +#define SYS_SDER32_EL2 sys_reg(3, 4, 1, 3, 1) +#define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0) +#define SYS_VSTTBR_EL2 sys_reg(3, 4, 2, 6, 0) +#define SYS_VSTCR_EL2 sys_reg(3, 4, 2, 6, 2) #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) @@ -514,6 +521,18 @@ #define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0) #define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0) +#define SYS_MPAMHCR_EL2 sys_reg(3, 4, 10, 4, 0) +#define SYS_MPAMVPMV_EL2 sys_reg(3, 4, 10, 4, 1) +#define SYS_MPAM2_EL2 sys_reg(3, 4, 10, 5, 0) +#define __SYS__MPAMVPMx_EL2(x) sys_reg(3, 4, 10, 6, x) +#define SYS_MPAMVPM0_EL2 __SYS__MPAMVPMx_EL2(0) +#define SYS_MPAMVPM1_EL2 __SYS__MPAMVPMx_EL2(1) +#define SYS_MPAMVPM2_EL2 __SYS__MPAMVPMx_EL2(2) +#define SYS_MPAMVPM3_EL2 __SYS__MPAMVPMx_EL2(3) +#define SYS_MPAMVPM4_EL2 __SYS__MPAMVPMx_EL2(4) +#define SYS_MPAMVPM5_EL2 __SYS__MPAMVPMx_EL2(5) +#define SYS_MPAMVPM6_EL2 __SYS__MPAMVPMx_EL2(6) +#define SYS_MPAMVPM7_EL2 __SYS__MPAMVPMx_EL2(7) #define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0) #define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1) @@ -562,9 +581,29 @@ #define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1) #define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2) +#define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7) + +#define __AMEV_op2(m) (m & 0x7) +#define __AMEV_CRm(n, m) (n | ((m & 0x8) >> 3)) +#define __SYS__AMEVCNTVOFF0n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m)) +#define SYS_AMEVCNTVOFF0n_EL2(m) __SYS__AMEVCNTVOFF0n_EL2(m) +#define __SYS__AMEVCNTVOFF1n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m)) +#define SYS_AMEVCNTVOFF1n_EL2(m) __SYS__AMEVCNTVOFF1n_EL2(m) #define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3) #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0) +#define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0) +#define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1) +#define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2) +#define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0) +#define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1) +#define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2) +#define SYS_CNTHVS_TVAL_EL2 sys_reg(3, 4, 14, 4, 0) +#define SYS_CNTHVS_CTL_EL2 sys_reg(3, 4, 14, 4, 1) +#define SYS_CNTHVS_CVAL_EL2 sys_reg(3, 4, 14, 4, 2) +#define SYS_CNTHPS_TVAL_EL2 sys_reg(3, 4, 14, 5, 0) +#define SYS_CNTHPS_CTL_EL2 sys_reg(3, 4, 14, 5, 1) +#define SYS_CNTHPS_CVAL_EL2 sys_reg(3, 4, 14, 5, 2) /* VHE encodings for architectural EL0/1 system registers */ #define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
Some _EL2 encodings are missing. Add them. Signed-off-by: Miguel Luis <miguel.luis@oracle.com> --- arch/arm64/include/asm/sysreg.h | 39 +++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)