| Message ID | 20231016175532.2081344-3-robimarko@gmail.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [1/3] dt-bindings: cpufreq: qcom-cpufreq-nvmem: document IPQ6018 | expand |
On 10/16/23 19:55, Robert Marko wrote: > IPQ6018 comes in multiple SKU-s and some of them dont support all of the > OPP-s that are current set, so lets utilize CPUFreq NVMEM to allow only > supported OPP-s based on the SoC dynamically. > > As an example, IPQ6018 is generaly rated at 1.8GHz but some silicon only > goes up to 1.5GHz and is marked as such via an eFuse. > > Signed-off-by: Robert Marko <robimarko@gmail.com> > --- > arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi > index 9aec89d5e095b..49f0e6aa4b5bb 100644 > --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi > @@ -96,42 +96,49 @@ scm { > }; > [...] > + cpu_speed_bin: cpu_speed_bin@135 { underscore -> minus sign Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
On 17/10/2023 18:55, Konrad Dybcio wrote: > > > On 10/16/23 19:55, Robert Marko wrote: >> IPQ6018 comes in multiple SKU-s and some of them dont support all of the >> OPP-s that are current set, so lets utilize CPUFreq NVMEM to allow only >> supported OPP-s based on the SoC dynamically. >> >> As an example, IPQ6018 is generaly rated at 1.8GHz but some silicon only >> goes up to 1.5GHz and is marked as such via an eFuse. >> >> Signed-off-by: Robert Marko <robimarko@gmail.com> >> --- >> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 +++++++++++++- >> 1 file changed, 13 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi >> index 9aec89d5e095b..49f0e6aa4b5bb 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi >> @@ -96,42 +96,49 @@ scm { >> }; >> > [...] > >> + cpu_speed_bin: cpu_speed_bin@135 { > underscore -> minus sign > > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> I think Bjorn does not read comments, so he just picks up such patches because they got review. Better to ask for fixing it, instead of giving conditional review tag, IMHO. Best regards, Krzysztof
On Tue, 17 Oct 2023 at 19:13, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 17/10/2023 18:55, Konrad Dybcio wrote: > > > > > > On 10/16/23 19:55, Robert Marko wrote: > >> IPQ6018 comes in multiple SKU-s and some of them dont support all of the > >> OPP-s that are current set, so lets utilize CPUFreq NVMEM to allow only > >> supported OPP-s based on the SoC dynamically. > >> > >> As an example, IPQ6018 is generaly rated at 1.8GHz but some silicon only > >> goes up to 1.5GHz and is marked as such via an eFuse. > >> > >> Signed-off-by: Robert Marko <robimarko@gmail.com> > >> --- > >> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 +++++++++++++- > >> 1 file changed, 13 insertions(+), 1 deletion(-) > >> > >> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi > >> index 9aec89d5e095b..49f0e6aa4b5bb 100644 > >> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi > >> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi > >> @@ -96,42 +96,49 @@ scm { > >> }; > >> > > [...] > > > >> + cpu_speed_bin: cpu_speed_bin@135 { > > underscore -> minus sign > > > > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > > I think Bjorn does not read comments, so he just picks up such patches > because they got review. Better to ask for fixing it, instead of giving > conditional review tag, IMHO. I will fix it up in v2, I am just waiting to see if there are comments on the driver patch. Regards, Robert > > Best regards, > Krzysztof >
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 9aec89d5e095b..49f0e6aa4b5bb 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -96,42 +96,49 @@ scm { }; cpu_opp_table: opp-table-cpu { - compatible = "operating-points-v2"; + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&cpu_speed_bin>; opp-shared; opp-864000000 { opp-hz = /bits/ 64 <864000000>; opp-microvolt = <725000>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-1056000000 { opp-hz = /bits/ 64 <1056000000>; opp-microvolt = <787500>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-1320000000 { opp-hz = /bits/ 64 <1320000000>; opp-microvolt = <862500>; + opp-supported-hw = <0x3>; clock-latency-ns = <200000>; }; opp-1440000000 { opp-hz = /bits/ 64 <1440000000>; opp-microvolt = <925000>; + opp-supported-hw = <0x3>; clock-latency-ns = <200000>; }; opp-1608000000 { opp-hz = /bits/ 64 <1608000000>; opp-microvolt = <987500>; + opp-supported-hw = <0x1>; clock-latency-ns = <200000>; }; opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <1062500>; + opp-supported-hw = <0x1>; clock-latency-ns = <200000>; }; }; @@ -314,6 +321,11 @@ qfprom: efuse@a4000 { reg = <0x0 0x000a4000 0x0 0x2000>; #address-cells = <1>; #size-cells = <1>; + + cpu_speed_bin: cpu_speed_bin@135 { + reg = <0x135 0x1>; + bits = <7 1>; + }; }; prng: qrng@e3000 {
IPQ6018 comes in multiple SKU-s and some of them dont support all of the OPP-s that are current set, so lets utilize CPUFreq NVMEM to allow only supported OPP-s based on the SoC dynamically. As an example, IPQ6018 is generaly rated at 1.8GHz but some silicon only goes up to 1.5GHz and is marked as such via an eFuse. Signed-off-by: Robert Marko <robimarko@gmail.com> --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-)