| Message ID | 20231018052654.50074-3-hch@lst.de (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 381cae1698538ad2f90dd6ecd8ed155d194e072f |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | [1/3] riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT | expand |
On 2023-10-18 12:26 AM, Christoph Hellwig wrote: > RISCV_DMA_NONCOHERENT is also used for whacky non-standard > non-coherent ops that use different hooks in dma-direct. > > Signed-off-by: Christoph Hellwig <hch@lst.de> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > Reviewed-by: Robin Murphy <robin.murphy@arm.com> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > arch/riscv/Kconfig | 2 +- > arch/riscv/Kconfig.errata | 1 + > 2 files changed, 2 insertions(+), 1 deletion(-) Tested-by: Samuel Holland <samuel.holland@sifive.com>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 0ac0b538379718..9c48fecc671918 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -273,7 +273,6 @@ config RISCV_DMA_NONCOHERENT select ARCH_HAS_SYNC_DMA_FOR_CPU select ARCH_HAS_SYNC_DMA_FOR_DEVICE select DMA_BOUNCE_UNALIGNED_KMALLOC if SWIOTLB - select DMA_DIRECT_REMAP if MMU config RISCV_NONSTANDARD_CACHE_OPS bool @@ -549,6 +548,7 @@ config RISCV_ISA_ZICBOM depends on RISCV_ALTERNATIVE default y select RISCV_DMA_NONCOHERENT + select DMA_DIRECT_REMAP help Adds support to dynamically detect the presence of the ZICBOM extension (Cache Block Management Operations) and enable its diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index 566bcefeab502c..e2c731cfed8cc6 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -77,6 +77,7 @@ config ERRATA_THEAD_PBMT config ERRATA_THEAD_CMO bool "Apply T-Head cache management errata" depends on ERRATA_THEAD && MMU + select DMA_DIRECT_REMAP select RISCV_DMA_NONCOHERENT default y help