| Message ID | 20230708072835.3035398-7-quic_jprakash@quicinc.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | iio: adc: Add support for QCOM SPMI PMIC5 Gen3 ADC | expand |
On Sat, 8 Jul 2023 12:58:30 +0530 Jishnu Prakash <quic_jprakash@quicinc.com> wrote: > For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the > following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. > It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs > going through PBS firmware through a single register interface. This > interface is implemented on an SDAM peripheral on the master PMIC PMK8550 > rather than a dedicated ADC peripheral. > > Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com> > --- > .../bindings/iio/adc/qcom,spmi-vadc.yaml | 117 ++++++++++++++++-- > .../iio/qcom,spmi-adc5-gen3-pm8550.h | 48 +++++++ > .../iio/qcom,spmi-adc5-gen3-pm8550b.h | 97 +++++++++++++++ > .../iio/qcom,spmi-adc5-gen3-pm8550vx.h | 20 +++ > .../iio/qcom,spmi-adc5-gen3-pmk8550.h | 54 ++++++++ > include/dt-bindings/iio/qcom,spmi-vadc.h | 78 ++++++++++++ > 6 files changed, 402 insertions(+), 12 deletions(-) > create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h > create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h > create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h > create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h > > diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml > index eb7d16e385ad..090113e62d52 100644 > --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml > +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml > @@ -13,8 +13,8 @@ maintainers: > description: | > SPMI PMIC voltage ADC (VADC) provides interface to clients to read > voltage. The VADC is a 15-bit sigma-delta ADC. > - SPMI PMIC5/PMIC5 Gen2 voltage ADC (ADC) provides interface to clients to read > - voltage. The VADC is a 16-bit sigma-delta ADC. > + SPMI PMIC5/PMIC5 Gen2/PMIC5 Gen3 voltage ADC (ADC) provides interface to > + clients to read voltage. The VADC is a 16-bit sigma-delta ADC. > > properties: > compatible: > @@ -27,10 +27,11 @@ properties: > - qcom,spmi-adc5 > - qcom,spmi-adc-rev2 > - qcom,spmi-adc5-gen2 > + - qcom,spmi-adc5-gen3 > > reg: > description: VADC base address in the SPMI PMIC register map > - maxItems: 1 > + minItems: 1 ? > > '#address-cells': > const: 1 > @@ -38,6 +39,12 @@ properties: > '#size-cells': > const: 0 > > + "#thermal-sensor-cells": > + const: 1 > + description: > + Number of cells required to uniquely identify the thermal sensors. Since > + we have multiple sensors this is set to 1. > + Defined only for the new gen3? If so make make it false for the other devices. > '#io-channel-cells': > const: 1 > > @@ -71,8 +78,8 @@ patternProperties: > description: | > ADC channel number. > See include/dt-bindings/iio/qcom,spmi-vadc.h > - For PMIC5 Gen2 ADC, the channel numbers are specified separately per PMIC > - in the PMIC-specific files in include/dt-bindings/iio/. > + For PMIC5 Gen2 and PMIC5 Gen3 ADC, the channel numbers are specified separately per > + PMIC in the PMIC-specific files in include/dt-bindings/iio/. > > label: > $ref: /schemas/types.yaml#/definitions/string > @@ -114,11 +121,12 @@ patternProperties: > channel calibration. If property is not found, channel will be > calibrated with 0.625V and 1.25V reference channels, also > known as absolute calibration. > - - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc5-gen2" and > - "qcom,spmi-adc-rev2", if this property is specified VADC will use > - the VDD reference (1.875V) and GND for channel calibration. If > - property is not found, channel will be calibrated with 0V and 1.25V > - reference channels, also known as absolute calibration. > + - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc5-gen2", > + "qcom,spmi-adc-rev2" and "qcom,spmi-adc5-gen3", if this property > + is specified VADC will use the VDD reference (1.875V) and GND for > + channel calibration. If property is not found, channel will be > + calibrated with 0V and 1.25V reference channels, also known as > + absolute calibration. > type: boolean > > qcom,hw-settle-time: > @@ -136,6 +144,12 @@ patternProperties: > from the ADC that is an average of multiple samples. The value > selected is 2^(value). > > + qcom,adc-tm-type: > + description: | > + Indicates if ADC_TM monitoring is done on this channel. > + Defined for compatible property "qcom,spmi-adc5-gen3". > + type: boolean Enforce that in the binding, not via a comment. Once the binding performs that check (set it to false for non matching compatibles) then there is no need to also mention it in text. > + > required: > - reg > > @@ -213,7 +227,9 @@ allOf: > properties: > compatible: > contains: > - const: qcom,spmi-adc5-gen2 > + enum: > + - qcom,spmi-adc5-gen2 > + - qcom,spmi-adc5-gen3 Side note - it's fine to have a single element enum, so you could use that option to reduce churn in this set... > > then: > patternProperties: > @@ -299,7 +315,7 @@ examples: > label = "xo_therm"; > }; > > - channel@47 { > + channel@147 { ? If that's a valid change, then it looks like a separate fix. > reg = <PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(1)>; > qcom,ratiometric; > qcom,hw-settle-time = <200>; > @@ -307,3 +323,80 @@ examples: > }; > }; > }; > + > + - | > + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h> > + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h> > + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h> > + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h> > + > + pmic { > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* VADC node */ > + pmk8550_vadc: vadc@9000 { > + compatible = "qcom,spmi-adc5-gen3"; > + reg = <0x9000>; > + interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>; > + #address-cells = <1>; > + #size-cells = <0>; > + #io-channel-cells = <1>; > + #thermal-sensor-cells = <1>; > + > + /* PMK8550 Channel nodes */ > + channel@3 { > + reg = <PMK8550_ADC5_GEN3_DIE_TEMP>; > + label = "pmk8550_die_temp"; > + qcom,pre-scaling = <1 1>; > + }; > + > + channel@44 { > + reg = <PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU>; > + label = "pmk8550_xo_therm"; > + qcom,pre-scaling = <1 1>; > + qcom,ratiometric; > + qcom,hw-settle-time = <200>; > + qcom,adc-tm-type; > + }; > + > + /* PM8550 Channel nodes */ > + channel@103 { > + reg = <PM8550_ADC5_GEN3_DIE_TEMP>; > + label = "pm8550_die_temp"; > + qcom,pre-scaling = <1 1>; > + }; > + > + channel@18e { > + reg = <PM8550_ADC5_GEN3_VPH_PWR>; > + label = "pm8550_vph_pwr"; > + qcom,pre-scaling = <1 3>; > + }; > + > + /* PM8550B Channel nodes */ > + channel@703 { > + reg = <PM8550B_ADC5_GEN3_DIE_TEMP>; > + label = "pm8550b_die_temp"; > + qcom,pre-scaling = <1 1>; > + }; > + > + channel@78e { > + reg = <PM8550B_ADC5_GEN3_VPH_PWR>; > + label = "pm8550b_vph_pwr"; > + qcom,pre-scaling = <1 3>; > + }; > + > + channel@78f { > + reg = <PM8550B_ADC5_GEN3_VBAT_SNS_QBG>; > + label = "pm8550b_vbat_sns_qbg"; > + qcom,pre-scaling = <1 3>; > + }; > + > + /* PM8550VS_C Channel nodes */ > + channel@203 { > + reg = <PM8550VS_ADC5_GEN3_DIE_TEMP(2)>; > + label = "pm8550vs_c_die_temp"; > + qcom,pre-scaling = <1 1>; > + }; > + }; > + }; > diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h > new file mode 100644 > index 000000000000..74e6e2f6f9ed > --- /dev/null > +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h > @@ -0,0 +1,48 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H > +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H > + > +#ifndef PM8550_SID > +#define PM8550_SID 1 > +#endif > + > +/* ADC channels for PM8550_ADC for PMIC5 Gen3 */ > +#define PM8550_ADC5_GEN3_OFFSET_REF (PM8550_SID << 8 | 0x00) can we do the naming for the 0x00 as per Dmitry's set? That is get them from qcom,spmi-vadc.h https://patchwork.kernel.org/project/linux-iio/patch/20230707123027.1510723-2-dmitry.baryshkov@linaro.org/ > +#define PM8550_ADC5_GEN3_1P25VREF (PM8550_SID << 8 | 0x01) > +#define PM8550_ADC5_GEN3_VREF_VADC (PM8550_SID << 8 | 0x02) > +#define PM8550_ADC5_GEN3_DIE_TEMP (PM8550_SID << 8 | 0x03) > + > diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h > index b1413c62ad27..ca5a0a947b3b 100644 > --- a/include/dt-bindings/iio/qcom,spmi-vadc.h > +++ b/include/dt-bindings/iio/qcom,spmi-vadc.h > @@ -298,4 +298,82 @@ > #define ADC5_GEN2_SBUx 0x94 > #define ADC5_GEN2_VBAT_2S_MID 0x96 > > +/* ADC channels for PMIC5 Gen3 */ > + > +#define ADC5_GEN3_OFFSET_REF 0x00 > +#define ADC5_GEN3_1P25VREF 0x01 > +#define ADC5_GEN3_VREF_VADC 0x02 > +#define ADC5_GEN3_DIE_TEMP 0x03
> > properties: > > compatible: > > @@ -27,10 +27,11 @@ properties: > > - qcom,spmi-adc5 > > - qcom,spmi-adc-rev2 > > - qcom,spmi-adc5-gen2 > > + - qcom,spmi-adc5-gen3 > > > > reg: > > description: VADC base address in the SPMI PMIC register map > > - maxItems: 1 > > + minItems: 1 > > ? Found it now. This needs documentation that it's providing multiple base addresses for gen3. Also needs to only apply that to gen3...
On 08/07/2023 09:28, Jishnu Prakash wrote: > For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the > following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. > It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs > going through PBS firmware through a single register interface. This > interface is implemented on an SDAM peripheral on the master PMIC PMK8550 > rather than a dedicated ADC peripheral. > > Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com> > --- > .../bindings/iio/adc/qcom,spmi-vadc.yaml | 117 ++++++++++++++++-- > .../iio/qcom,spmi-adc5-gen3-pm8550.h | 48 +++++++ > .../iio/qcom,spmi-adc5-gen3-pm8550b.h | 97 +++++++++++++++ > .../iio/qcom,spmi-adc5-gen3-pm8550vx.h | 20 +++ > .../iio/qcom,spmi-adc5-gen3-pmk8550.h | 54 ++++++++ > include/dt-bindings/iio/qcom,spmi-vadc.h | 78 ++++++++++++ > 6 files changed, 402 insertions(+), 12 deletions(-) > create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h > create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h > create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h > create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h > > diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml > index eb7d16e385ad..090113e62d52 100644 > --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml > +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml > @@ -13,8 +13,8 @@ maintainers: > description: | > SPMI PMIC voltage ADC (VADC) provides interface to clients to read > voltage. The VADC is a 15-bit sigma-delta ADC. > - SPMI PMIC5/PMIC5 Gen2 voltage ADC (ADC) provides interface to clients to read > - voltage. The VADC is a 16-bit sigma-delta ADC. > + SPMI PMIC5/PMIC5 Gen2/PMIC5 Gen3 voltage ADC (ADC) provides interface to > + clients to read voltage. The VADC is a 16-bit sigma-delta ADC. > > properties: > compatible: > @@ -27,10 +27,11 @@ properties: > - qcom,spmi-adc5 > - qcom,spmi-adc-rev2 > - qcom,spmi-adc5-gen2 > + - qcom,spmi-adc5-gen3 This could be ordered... > > reg: > description: VADC base address in the SPMI PMIC register map > - maxItems: 1 > + minItems: 1 Why? This does not make any sense. With previous patches it looks like random set of changes. > > '#address-cells': > const: 1 > @@ -38,6 +39,12 @@ properties: > '#size-cells': > const: 0 > > + "#thermal-sensor-cells": > + const: 1 > + description: > + Number of cells required to uniquely identify the thermal sensors. Since > + we have multiple sensors this is set to 1. > + > '#io-channel-cells': > const: 1 > > @@ -71,8 +78,8 @@ patternProperties: > description: | > ADC channel number. > See include/dt-bindings/iio/qcom,spmi-vadc.h > - For PMIC5 Gen2 ADC, the channel numbers are specified separately per PMIC > - in the PMIC-specific files in include/dt-bindings/iio/. > + For PMIC5 Gen2 and PMIC5 Gen3 ADC, the channel numbers are specified separately per > + PMIC in the PMIC-specific files in include/dt-bindings/iio/. > > label: > $ref: /schemas/types.yaml#/definitions/string > @@ -114,11 +121,12 @@ patternProperties: > channel calibration. If property is not found, channel will be > calibrated with 0.625V and 1.25V reference channels, also > known as absolute calibration. > - - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc5-gen2" and > - "qcom,spmi-adc-rev2", if this property is specified VADC will use > - the VDD reference (1.875V) and GND for channel calibration. If > - property is not found, channel will be calibrated with 0V and 1.25V > - reference channels, also known as absolute calibration. > + - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc5-gen2", > + "qcom,spmi-adc-rev2" and "qcom,spmi-adc5-gen3", if this property > + is specified VADC will use the VDD reference (1.875V) and GND for > + channel calibration. If property is not found, channel will be > + calibrated with 0V and 1.25V reference channels, also known as > + absolute calibration. > type: boolean > > qcom,hw-settle-time: > @@ -136,6 +144,12 @@ patternProperties: > from the ADC that is an average of multiple samples. The value > selected is 2^(value). > > + qcom,adc-tm-type: > + description: | > + Indicates if ADC_TM monitoring is done on this channel. Description does not match property name. > + Defined for compatible property "qcom,spmi-adc5-gen3". Then you need if:then:. > + type: boolean > + > required: > - reg > > @@ -213,7 +227,9 @@ allOf: > properties: > compatible: > contains: > - const: qcom,spmi-adc5-gen2 > + enum: > + - qcom,spmi-adc5-gen2 > + - qcom,spmi-adc5-gen3 > > then: > patternProperties: > @@ -299,7 +315,7 @@ examples: > label = "xo_therm"; > }; > > - channel@47 { > + channel@147 { Why? > reg = <PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(1)>; > qcom,ratiometric; > qcom,hw-settle-time = <200>; > @@ -307,3 +323,80 @@ examples: > }; > }; > }; > + > + - | > + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h> > + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h> > + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h> > + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h> > + > + pmic { > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* VADC node */ > + pmk8550_vadc: vadc@9000 { > + compatible = "qcom,spmi-adc5-gen3"; Don't add new examples which differ only in compatible. > diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h > new file mode 100644 > index 000000000000..74e6e2f6f9ed > --- /dev/null > +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h > @@ -0,0 +1,48 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ Dual license. Best regards, Krzysztof
Hi Jonathan, On 7/8/2023 8:42 PM, Jonathan Cameron wrote: > On Sat, 8 Jul 2023 12:58:30 +0530 > Jishnu Prakash <quic_jprakash@quicinc.com> wrote: > >> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the >> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. >> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs >> >> reg: >> description: VADC base address in the SPMI PMIC register map >> - maxItems: 1 >> + minItems: 1 > ? The idea here is to convey that reg can have multiple values for ADC5 Gen3 as there can be more than one peripheral used for ADC, so there can be multiple base addresses. I'll try to make this more clear in the next patchset. > >> >> '#address-cells': >> const: 1 >> @@ -38,6 +39,12 @@ properties: >> '#size-cells': >> const: 0 >> >> + "#thermal-sensor-cells": >> + const: 1 >> + description: >> + Number of cells required to uniquely identify the thermal sensors. Since >> + we have multiple sensors this is set to 1. >> + > Defined only for the new gen3? If so make make it false for the other devices. Yes, will do that in the next patchset. > >> '#io-channel-cells': >> const: 1 >> >> @@ -71,8 +78,8 @@ patternProperties: >> description: | >> ADC channel number. >> >> + qcom,adc-tm-type: >> + description: | >> + Indicates if ADC_TM monitoring is done on this channel. >> + Defined for compatible property "qcom,spmi-adc5-gen3". >> + type: boolean > Enforce that in the binding, not via a comment. Once the binding > performs that check (set it to false for non matching compatibles) then > there is no need to also mention it in text. Will do that in the next patchset. > >> + >> required: >> - reg >> >> @@ -213,7 +227,9 @@ allOf: >> properties: >> compatible: >> contains: >> - const: qcom,spmi-adc5-gen2 >> + enum: >> + - qcom,spmi-adc5-gen2 >> + - qcom,spmi-adc5-gen3 > Side note - it's fine to have a single element enum, so you could > use that option to reduce churn in this set... I think we can remove this and instead specify properties explicitly for qcom,spmi-adc5-gen3 too separately in the next patchset. > >> >> then: >> patternProperties: >> @@ -299,7 +315,7 @@ examples: >> label = "xo_therm"; >> }; >> >> - channel@47 { >> + channel@147 { > ? If that's a valid change, then it looks like a separate fix. I think I can avoid this for now, although it would be needed if this channel number was the virtual channel number made by combining PMIC SID and actual channel number....maybe we can do it in a separate fix. > >> reg = <PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(1)>; >> qcom,ratiometric; >> qcom,hw-settle-time = <200>; >> @@ -307,3 +323,80 @@ examples: >> }; >> }; >> }; >> + >> +#ifndef PM8550_SID >> +#define PM8550_SID 1 >> +#endif >> + >> +/* ADC channels for PM8550_ADC for PMIC5 Gen3 */ >> +#define PM8550_ADC5_GEN3_OFFSET_REF (PM8550_SID << 8 | 0x00) > can we do the naming for the 0x00 as per Dmitry's set? That is get them from > qcom,spmi-vadc.h > > https://patchwork.kernel.org/project/linux-iio/patch/20230707123027.1510723-2-dmitry.baryshkov@linaro.org/ Yes, will do that in the next patchset. Thanks, Jishnu
Hi Jonathan, On 7/8/2023 8:55 PM, Jonathan Cameron wrote: >>> properties: >>> compatible: >>> @@ -27,10 +27,11 @@ properties: >>> - qcom,spmi-adc5 >>> - qcom,spmi-adc-rev2 >>> - qcom,spmi-adc5-gen2 >>> + - qcom,spmi-adc5-gen3 >>> >>> reg: >>> description: VADC base address in the SPMI PMIC register map >>> - maxItems: 1 >>> + minItems: 1 >> ? > Found it now. This needs documentation that it's providing multiple > base addresses for gen3. Also needs to only apply that to gen3... > Yes, I'll do that in the next patchset. Thanks, Jishnu
Hi Krzysztof, On 7/9/2023 10:53 PM, Krzysztof Kozlowski wrote: > On 08/07/2023 09:28, Jishnu Prakash wrote: >> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the >> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. >> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs >> going through PBS firmware through a single register interface. This >> interface is implemented on an SDAM peripheral on the master PMIC PMK8550 >> rather than a dedicated ADC peripheral. >> >> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com> >> --- >> properties: >> compatible: >> @@ -27,10 +27,11 @@ properties: >> - qcom,spmi-adc5 >> - qcom,spmi-adc-rev2 >> - qcom,spmi-adc5-gen2 >> + - qcom,spmi-adc5-gen3 > > This could be ordered... Yes, will do that in the next patchset. >> >> reg: >> description: VADC base address in the SPMI PMIC register map >> - maxItems: 1 >> + minItems: 1 > Why? This does not make any sense. With previous patches it looks like > random set of changes. The idea here is to convey that reg can have multiple values for ADC5 Gen3 as there can be more than one peripheral used for ADC, so there can be multiple base addresses. I'll try to make this more clear in the next patchset. > > >> >> '#address-cells': >> const: 1 >> @@ -38,6 +39,12 @@ properties: >> '#size-cells': >> const: 0 >> >> >> + qcom,adc-tm-type: >> + description: | >> + Indicates if ADC_TM monitoring is done on this channel. > Description does not match property name. You mean it sounds more like an enum which can take several values rather than just a boolean? I can update it to "qcom,adc-tm" if that looks better. > >> + Defined for compatible property "qcom,spmi-adc5-gen3". > Then you need if:then:. Yes, will update this explicitly for ADC5 Gen3 in the next patchset. > >> + type: boolean >> + >> required: >> - reg >> >> @@ -213,7 +227,9 @@ allOf: >> properties: >> compatible: >> contains: >> - const: qcom,spmi-adc5-gen2 >> + enum: >> + - qcom,spmi-adc5-gen2 >> + - qcom,spmi-adc5-gen3 >> >> then: >> patternProperties: >> @@ -299,7 +315,7 @@ examples: >> label = "xo_therm"; >> }; >> >> - channel@47 { >> + channel@147 { > Why? It would be needed if this channel number was supposed to be the virtual channel number made by combining PMIC SID and actual channel number....but I could drop it for now and do it in a separate fix as Jonathan suggested. > >> reg = <PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(1)>; >> qcom,ratiometric; >> qcom,hw-settle-time = <200>; >> @@ -307,3 +323,80 @@ examples: >> }; >> }; >> }; >> + >> + - | >> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h> >> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h> >> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h> >> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h> >> + >> + pmic { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + /* VADC node */ >> + pmk8550_vadc: vadc@9000 { >> + compatible = "qcom,spmi-adc5-gen3"; > Don't add new examples which differ only in compatible. This example does have differences unique to ADC5 Gen3 such as use of "#thermal-sensor-cells" and "qcom,adc-tm-type" properties....to make it clearer, I'll delete some of the excess nodes which don't highlight these differences. > > >> diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h >> new file mode 100644 >> index 000000000000..74e6e2f6f9ed >> --- /dev/null >> +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h >> @@ -0,0 +1,48 @@ >> +/* SPDX-License-Identifier: GPL-2.0-only */ > Dual license. I think we do have an internal rule by which we do have to add these two licenses....I'll check again and update them if required. Thanks, Jishnu > > > > Best regards, > Krzysztof >
On 23/10/2023 08:14, Jishnu Prakash wrote: > Hi Krzysztof, > > On 7/9/2023 10:53 PM, Krzysztof Kozlowski wrote: >> On 08/07/2023 09:28, Jishnu Prakash wrote: >>> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the >>> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. >>> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs >>> going through PBS firmware through a single register interface. This >>> interface is implemented on an SDAM peripheral on the master PMIC PMK8550 >>> rather than a dedicated ADC peripheral. >>> >>> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com> >>> --- >>> properties: >>> compatible: >>> @@ -27,10 +27,11 @@ properties: >>> - qcom,spmi-adc5 >>> - qcom,spmi-adc-rev2 >>> - qcom,spmi-adc5-gen2 >>> + - qcom,spmi-adc5-gen3 >> >> This could be ordered... > > > Yes, will do that in the next patchset. > > >>> >>> reg: >>> description: VADC base address in the SPMI PMIC register map >>> - maxItems: 1 >>> + minItems: 1 >> Why? This does not make any sense. With previous patches it looks like >> random set of changes. > > > The idea here is to convey that reg can have multiple values for ADC5 > Gen3 as there can be more than one peripheral used for ADC, so there can > be multiple base addresses. I'll try to make this more clear in the next > patchset. You cannot remove constraints from an entry. > > >> >> >>> >>> '#address-cells': >>> const: 1 >>> @@ -38,6 +39,12 @@ properties: >>> '#size-cells': >>> const: 0 >>> >>> >>> + qcom,adc-tm-type: >>> + description: | >>> + Indicates if ADC_TM monitoring is done on this channel. >> Description does not match property name. > > > You mean it sounds more like an enum which can take several values > rather than just a boolean? I can update it to "qcom,adc-tm" if that > looks better. The property name suggests this is type of monitoring. Property description says this will enable ADC_TM monitoring. These two do not match. Except that I wonder now whether this is a property of hardware at all... What is this monitoring? By the driver? ... >>> then: >>> patternProperties: >>> @@ -299,7 +315,7 @@ examples: >>> label = "xo_therm"; >>> }; >>> >>> - channel@47 { >>> + channel@147 { >> Why? > > > It would be needed if this channel number was supposed to be the virtual > channel number made by combining PMIC SID and actual channel > number....but I could drop it for now and do it in a separate fix as > Jonathan suggested. > > >> >>> reg = <PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(1)>; >>> qcom,ratiometric; >>> qcom,hw-settle-time = <200>; >>> @@ -307,3 +323,80 @@ examples: >>> }; >>> }; >>> }; >>> + >>> + - | >>> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h> >>> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h> >>> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h> >>> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h> >>> + >>> + pmic { >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + /* VADC node */ >>> + pmk8550_vadc: vadc@9000 { >>> + compatible = "qcom,spmi-adc5-gen3"; >> Don't add new examples which differ only in compatible. > > > This example does have differences unique to ADC5 Gen3 such as use of > "#thermal-sensor-cells" and "qcom,adc-tm-type" properties....to make it > clearer, I'll delete some of the excess nodes which don't highlight > these differences. > > >> >> >>> diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h >>> new file mode 100644 >>> index 000000000000..74e6e2f6f9ed >>> --- /dev/null >>> +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h >>> @@ -0,0 +1,48 @@ >>> +/* SPDX-License-Identifier: GPL-2.0-only */ >> Dual license. > > > I think we do have an internal rule by which we do have to add these two > licenses....I'll check again and update them if required. Just to be clear: your internal rules are your internal affair. We expect here dual license. Best regards, Krzysztof
Hi Krzysztof, On 10/23/2023 12:06 PM, Krzysztof Kozlowski wrote: > On 23/10/2023 08:14, Jishnu Prakash wrote: >> Hi Krzysztof, >> >> On 7/9/2023 10:53 PM, Krzysztof Kozlowski wrote: >> >>>> reg: >>>> description: VADC base address in the SPMI PMIC register map >>>> - maxItems: 1 >>>> + minItems: 1 >>> Why? This does not make any sense. With previous patches it looks like >>> random set of changes. >> The idea here is to convey that reg can have multiple values for ADC5 >> Gen3 as there can be more than one peripheral used for ADC, so there can >> be multiple base addresses. I'll try to make this more clear in the next >> patchset. > You cannot remove constraints from an entry. In this case, minItems: 1 will remain true for all other ADC devices documented here, but it will not be true for ADC5 Gen3, as this one can have multiple base addresses if more than one SDAM is used for ADC. I'll update this separately for each compatible, keeping it the same for the older ones, hope that should work. >>>> >>>> '#address-cells': >>>> const: 1 >>>> @@ -38,6 +39,12 @@ properties: >>>> '#size-cells': >>>> const: 0 >>>> >>>> >>>> + qcom,adc-tm-type: >>>> + description: | >>>> + Indicates if ADC_TM monitoring is done on this channel. >>> Description does not match property name. >> You mean it sounds more like an enum which can take several values >> rather than just a boolean? I can update it to "qcom,adc-tm" if that >> looks better. > The property name suggests this is type of monitoring. Property > description says this will enable ADC_TM monitoring. These two do not match. > > Except that I wonder now whether this is a property of hardware at > all... What is this monitoring? By the driver? The property description is right, this property is used to indicate that one of the configurable channels on the ADC SDAMs will be used for ADC_TM functionality, for periodically monitoring this particular ADC channel . This is the exact same functionality as in the existing QCOM ADC_TM device, documented at devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml. I'll mention this too in the description. It can be considered a property of the hardware as the monitoring is done by a sequence under PBS (Programmable Boot Sequence, can be considered firmware), which periodically gets the channel reading and checks it against upper/lower thresholds set by clients of this driver, for threshold violations. > ... > >>>> then: >>>> patternProperties: >>>> @@ -299,7 +315,7 @@ examples: >>>> label = "xo_therm"; >>>> }; >>>> >>>> diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h >>>> new file mode 100644 >>>> index 000000000000..74e6e2f6f9ed >>>> --- /dev/null >>>> +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h >>>> @@ -0,0 +1,48 @@ >>>> +/* SPDX-License-Identifier: GPL-2.0-only */ >>> Dual license. >> I think we do have an internal rule by which we do have to add these two >> licenses....I'll check again and update them if required. > Just to be clear: your internal rules are your internal affair. We > expect here dual license. I misunderstood what you meant earlier, I understand now that "GPL-2.0-only" is wrong, I'll update it. Thanks, Jishnu > Best regards, > Krzysztof >
On 16/11/2023 04:23, Jishnu Prakash wrote: > Hi Krzysztof, > > On 10/23/2023 12:06 PM, Krzysztof Kozlowski wrote: >> On 23/10/2023 08:14, Jishnu Prakash wrote: >>> Hi Krzysztof, >>> >>> On 7/9/2023 10:53 PM, Krzysztof Kozlowski wrote: >>> >>>>> reg: >>>>> description: VADC base address in the SPMI PMIC register map >>>>> - maxItems: 1 >>>>> + minItems: 1 >>>> Why? This does not make any sense. With previous patches it looks like >>>> random set of changes. >>> The idea here is to convey that reg can have multiple values for ADC5 >>> Gen3 as there can be more than one peripheral used for ADC, so there can >>> be multiple base addresses. I'll try to make this more clear in the next >>> patchset. >> You cannot remove constraints from an entry. > > > In this case, minItems: 1 will remain true for all other ADC devices > documented here, but it will not be true for ADC5 Gen3, as this one can > have multiple base addresses if more than one SDAM is used for ADC. I'll > update this separately for each compatible, keeping it the same for the > older ones, hope that should work. You responded like you disagree with me, so just in case: my comment stays. If you resend the same, I will NAK it. > > >>>>> >>>>> '#address-cells': >>>>> const: 1 >>>>> @@ -38,6 +39,12 @@ properties: >>>>> '#size-cells': >>>>> const: 0 >>>>> >>>>> >>>>> + qcom,adc-tm-type: >>>>> + description: | >>>>> + Indicates if ADC_TM monitoring is done on this channel. >>>> Description does not match property name. >>> You mean it sounds more like an enum which can take several values >>> rather than just a boolean? I can update it to "qcom,adc-tm" if that >>> looks better. >> The property name suggests this is type of monitoring. Property >> description says this will enable ADC_TM monitoring. These two do not match. >> >> Except that I wonder now whether this is a property of hardware at >> all... What is this monitoring? By the driver? > > > The property description is right, this property is used to indicate > that one of the configurable channels on the ADC SDAMs will be used for > ADC_TM functionality, for periodically monitoring this particular ADC > channel . This is the exact same functionality as in the existing QCOM > ADC_TM device, documented at > devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml. I'll mention this > too in the description. > > It can be considered a property of the hardware as the monitoring is > done by a sequence under PBS (Programmable Boot Sequence, can be > considered firmware), which periodically gets the channel reading and > checks it against upper/lower thresholds set by clients of this driver, > for threshold violations. > > >> ... >> >>>>> then: >>>>> patternProperties: >>>>> @@ -299,7 +315,7 @@ examples: >>>>> label = "xo_therm"; >>>>> }; >>>>> > >>>>> diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h >>>>> new file mode 100644 >>>>> index 000000000000..74e6e2f6f9ed >>>>> --- /dev/null >>>>> +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h >>>>> @@ -0,0 +1,48 @@ >>>>> +/* SPDX-License-Identifier: GPL-2.0-only */ >>>> Dual license. >>> I think we do have an internal rule by which we do have to add these two >>> licenses....I'll check again and update them if required. >> Just to be clear: your internal rules are your internal affair. We >> expect here dual license. > > > I misunderstood what you meant earlier, I understand now that > "GPL-2.0-only" is wrong, I'll update it. If only you run checkpatch before sending patches... Best regards, Krzysztof
On 16/11/2023 04:23, Jishnu Prakash wrote: > Hi Krzysztof, > > On 10/23/2023 12:06 PM, Krzysztof Kozlowski wrote: >> On 23/10/2023 08:14, Jishnu Prakash wrote: >>> Hi Krzysztof, >>> >>> On 7/9/2023 10:53 PM, Krzysztof Kozlowski wrote: >>> >>>>> reg: >>>>> description: VADC base address in the SPMI PMIC register map >>>>> - maxItems: 1 >>>>> + minItems: 1 >>>> Why? This does not make any sense. With previous patches it looks like >>>> random set of changes. >>> The idea here is to convey that reg can have multiple values for ADC5 >>> Gen3 as there can be more than one peripheral used for ADC, so there can >>> be multiple base addresses. I'll try to make this more clear in the next >>> patchset. >> You cannot remove constraints from an entry. > > > In this case, minItems: 1 will remain true for all other ADC devices > documented here, but it will not be true for ADC5 Gen3, as this one can > have multiple base addresses if more than one SDAM is used for ADC. I'll > update this separately for each compatible, keeping it the same for the > older ones, hope that should work. BTW, you disagree with me and send new version 2 minutes later. Basically you did not leave me any time to respond to you. That's not how the process works. Best regards, Krzysztof
Hi Krzysztof On 11/16/2023 5:16 PM, Krzysztof Kozlowski wrote: > On 16/11/2023 04:23, Jishnu Prakash wrote: >> Hi Krzysztof, >> >> On 10/23/2023 12:06 PM, Krzysztof Kozlowski wrote: >>> You cannot remove constraints from an entry. >> >> In this case, minItems: 1 will remain true for all other ADC devices >> documented here, but it will not be true for ADC5 Gen3, as this one can >> have multiple base addresses if more than one SDAM is used for ADC. I'll >> update this separately for each compatible, keeping it the same for the >> older ones, hope that should work. > BTW, you disagree with me and send new version 2 minutes later. > Basically you did not leave me any time to respond to you. > > That's not how the process works. Sorry about this, I'll make sure not to repeat this. Thanks, Jishnu > > Best regards, > Krzysztof >
diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml index eb7d16e385ad..090113e62d52 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml @@ -13,8 +13,8 @@ maintainers: description: | SPMI PMIC voltage ADC (VADC) provides interface to clients to read voltage. The VADC is a 15-bit sigma-delta ADC. - SPMI PMIC5/PMIC5 Gen2 voltage ADC (ADC) provides interface to clients to read - voltage. The VADC is a 16-bit sigma-delta ADC. + SPMI PMIC5/PMIC5 Gen2/PMIC5 Gen3 voltage ADC (ADC) provides interface to + clients to read voltage. The VADC is a 16-bit sigma-delta ADC. properties: compatible: @@ -27,10 +27,11 @@ properties: - qcom,spmi-adc5 - qcom,spmi-adc-rev2 - qcom,spmi-adc5-gen2 + - qcom,spmi-adc5-gen3 reg: description: VADC base address in the SPMI PMIC register map - maxItems: 1 + minItems: 1 '#address-cells': const: 1 @@ -38,6 +39,12 @@ properties: '#size-cells': const: 0 + "#thermal-sensor-cells": + const: 1 + description: + Number of cells required to uniquely identify the thermal sensors. Since + we have multiple sensors this is set to 1. + '#io-channel-cells': const: 1 @@ -71,8 +78,8 @@ patternProperties: description: | ADC channel number. See include/dt-bindings/iio/qcom,spmi-vadc.h - For PMIC5 Gen2 ADC, the channel numbers are specified separately per PMIC - in the PMIC-specific files in include/dt-bindings/iio/. + For PMIC5 Gen2 and PMIC5 Gen3 ADC, the channel numbers are specified separately per + PMIC in the PMIC-specific files in include/dt-bindings/iio/. label: $ref: /schemas/types.yaml#/definitions/string @@ -114,11 +121,12 @@ patternProperties: channel calibration. If property is not found, channel will be calibrated with 0.625V and 1.25V reference channels, also known as absolute calibration. - - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc5-gen2" and - "qcom,spmi-adc-rev2", if this property is specified VADC will use - the VDD reference (1.875V) and GND for channel calibration. If - property is not found, channel will be calibrated with 0V and 1.25V - reference channels, also known as absolute calibration. + - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc5-gen2", + "qcom,spmi-adc-rev2" and "qcom,spmi-adc5-gen3", if this property + is specified VADC will use the VDD reference (1.875V) and GND for + channel calibration. If property is not found, channel will be + calibrated with 0V and 1.25V reference channels, also known as + absolute calibration. type: boolean qcom,hw-settle-time: @@ -136,6 +144,12 @@ patternProperties: from the ADC that is an average of multiple samples. The value selected is 2^(value). + qcom,adc-tm-type: + description: | + Indicates if ADC_TM monitoring is done on this channel. + Defined for compatible property "qcom,spmi-adc5-gen3". + type: boolean + required: - reg @@ -213,7 +227,9 @@ allOf: properties: compatible: contains: - const: qcom,spmi-adc5-gen2 + enum: + - qcom,spmi-adc5-gen2 + - qcom,spmi-adc5-gen3 then: patternProperties: @@ -299,7 +315,7 @@ examples: label = "xo_therm"; }; - channel@47 { + channel@147 { reg = <PM8350_ADC5_GEN2_AMUX_THM4_100K_PU(1)>; qcom,ratiometric; qcom,hw-settle-time = <200>; @@ -307,3 +323,80 @@ examples: }; }; }; + + - | + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h> + #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h> + + pmic { + #address-cells = <1>; + #size-cells = <0>; + + /* VADC node */ + pmk8550_vadc: vadc@9000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x9000>; + interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + #thermal-sensor-cells = <1>; + + /* PMK8550 Channel nodes */ + channel@3 { + reg = <PMK8550_ADC5_GEN3_DIE_TEMP>; + label = "pmk8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@44 { + reg = <PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU>; + label = "pmk8550_xo_therm"; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,adc-tm-type; + }; + + /* PM8550 Channel nodes */ + channel@103 { + reg = <PM8550_ADC5_GEN3_DIE_TEMP>; + label = "pm8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@18e { + reg = <PM8550_ADC5_GEN3_VPH_PWR>; + label = "pm8550_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + /* PM8550B Channel nodes */ + channel@703 { + reg = <PM8550B_ADC5_GEN3_DIE_TEMP>; + label = "pm8550b_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@78e { + reg = <PM8550B_ADC5_GEN3_VPH_PWR>; + label = "pm8550b_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + channel@78f { + reg = <PM8550B_ADC5_GEN3_VBAT_SNS_QBG>; + label = "pm8550b_vbat_sns_qbg"; + qcom,pre-scaling = <1 3>; + }; + + /* PM8550VS_C Channel nodes */ + channel@203 { + reg = <PM8550VS_ADC5_GEN3_DIE_TEMP(2)>; + label = "pm8550vs_c_die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + }; diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h new file mode 100644 index 000000000000..74e6e2f6f9ed --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H + +#ifndef PM8550_SID +#define PM8550_SID 1 +#endif + +/* ADC channels for PM8550_ADC for PMIC5 Gen3 */ +#define PM8550_ADC5_GEN3_OFFSET_REF (PM8550_SID << 8 | 0x00) +#define PM8550_ADC5_GEN3_1P25VREF (PM8550_SID << 8 | 0x01) +#define PM8550_ADC5_GEN3_VREF_VADC (PM8550_SID << 8 | 0x02) +#define PM8550_ADC5_GEN3_DIE_TEMP (PM8550_SID << 8 | 0x03) + +#define PM8550_ADC5_GEN3_AMUX_THM1 (PM8550_SID << 8 | 0x04) +#define PM8550_ADC5_GEN3_AMUX_THM2 (PM8550_SID << 8 | 0x05) +#define PM8550_ADC5_GEN3_AMUX_THM3 (PM8550_SID << 8 | 0x06) +#define PM8550_ADC5_GEN3_AMUX_THM4 (PM8550_SID << 8 | 0x07) +#define PM8550_ADC5_GEN3_AMUX_THM5 (PM8550_SID << 8 | 0x08) +#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2 (PM8550_SID << 8 | 0x09) +#define PM8550_ADC5_GEN3_AMUX1_GPIO3 (PM8550_SID << 8 | 0x0a) +#define PM8550_ADC5_GEN3_AMUX2_GPIO4 (PM8550_SID << 8 | 0x0b) +#define PM8550_ADC5_GEN3_AMUX3_GPIO7 (PM8550_SID << 8 | 0x0c) +#define PM8550_ADC5_GEN3_AMUX4_GPIO12 (PM8550_SID << 8 | 0x0d) + +/* 100k pull-up */ +#define PM8550_ADC5_GEN3_AMUX_THM1_100K_PU (PM8550_SID << 8 | 0x44) +#define PM8550_ADC5_GEN3_AMUX_THM2_100K_PU (PM8550_SID << 8 | 0x45) +#define PM8550_ADC5_GEN3_AMUX_THM3_100K_PU (PM8550_SID << 8 | 0x46) +#define PM8550_ADC5_GEN3_AMUX_THM4_100K_PU (PM8550_SID << 8 | 0x47) +#define PM8550_ADC5_GEN3_AMUX_THM5_100K_PU (PM8550_SID << 8 | 0x48) +#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2_100K_PU (PM8550_SID << 8 | 0x49) +#define PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU (PM8550_SID << 8 | 0x4a) +#define PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU (PM8550_SID << 8 | 0x4b) +#define PM8550_ADC5_GEN3_AMUX3_GPIO7_100K_PU (PM8550_SID << 8 | 0x4c) +#define PM8550_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550_SID << 8 | 0x4d) + +/* 1/3 Divider */ +#define PM8550_ADC5_GEN3_AMUX3_GPIO7_DIV3 (PM8550_SID << 8 | 0x8c) +#define PM8550_ADC5_GEN3_AMUX4_GPIO12_DIV3 (PM8550_SID << 8 | 0x8d) + +#define PM8550_ADC5_GEN3_VPH_PWR (PM8550_SID << 8 | 0x8e) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h new file mode 100644 index 000000000000..35483dfd970e --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H + +#ifndef PM8550B_SID +#define PM8550B_SID 7 +#endif + +/* ADC channels for PM8550B_ADC for PMIC5 Gen3 */ +#define PM8550B_ADC5_GEN3_OFFSET_REF (PM8550B_SID << 8 | 0x00) +#define PM8550B_ADC5_GEN3_1P25VREF (PM8550B_SID << 8 | 0x01) +#define PM8550B_ADC5_GEN3_VREF_VADC (PM8550B_SID << 8 | 0x02) +#define PM8550B_ADC5_GEN3_DIE_TEMP (PM8550B_SID << 8 | 0x03) + +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM (PM8550B_SID << 8 | 0x04) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID (PM8550B_SID << 8 | 0x05) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V (PM8550B_SID << 8 | 0x06) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM (PM8550B_SID << 8 | 0x07) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION (PM8550B_SID << 8 | 0x08) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10 (PM8550B_SID << 8 | 0x09) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1 (PM8550B_SID << 8 | 0x0a) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5 (PM8550B_SID << 8 | 0x0b) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6 (PM8550B_SID << 8 | 0x0c) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12 (PM8550B_SID << 8 | 0x0d) + +#define PM8550B_ADC5_GEN3_CHG_TEMP (PM8550B_SID << 8 | 0x10) +#define PM8550B_ADC5_GEN3_USB_SNS_V_16 (PM8550B_SID << 8 | 0x11) +#define PM8550B_ADC5_GEN3_VIN_DIV16_MUX (PM8550B_SID << 8 | 0x12) +#define PM8550B_ADC5_GEN3_USBC_MUX (PM8550B_SID << 8 | 0x13) +#define PM8550B_ADC5_GEN3_VREF_BAT_THERM (PM8550B_SID << 8 | 0x15) +#define PM8550B_ADC5_GEN3_IIN_FB (PM8550B_SID << 8 | 0x17) +#define PM8550B_ADC5_GEN3_TEMP_ALARM_LITE (PM8550B_SID << 8 | 0x18) +#define PM8550B_ADC5_GEN3_SMB_IIN (PM8550B_SID << 8 | 0x19) +#define PM8550B_ADC5_GEN3_VREF_BAT2_THERM (PM8550B_SID << 8 | 0x1a) +#define PM8550B_ADC5_GEN3_SMB_ICHG (PM8550B_SID << 8 | 0x1b) +#define PM8550B_ADC5_GEN3_SMB_TEMP_I (PM8550B_SID << 8 | 0x1e) +#define PM8550B_ADC5_GEN3_CHG_TEMP_I (PM8550B_SID << 8 | 0x1f) +#define PM8550B_ADC5_GEN3_ICHG_FB (PM8550B_SID << 8 | 0xa1) + +/* 30k pull-up */ +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_30K_PU (PM8550B_SID << 8 | 0x24) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_30K_PU (PM8550B_SID << 8 | 0x25) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_30K_PU (PM8550B_SID << 8 | 0x26) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_30K_PU (PM8550B_SID << 8 | 0x27) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_30K_PU (PM8550B_SID << 8 | 0x28) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_30K_PU (PM8550B_SID << 8 | 0x29) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_30K_PU (PM8550B_SID << 8 | 0x2a) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_30K_PU (PM8550B_SID << 8 | 0x2b) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_30K_PU (PM8550B_SID << 8 | 0x2c) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_30K_PU (PM8550B_SID << 8 | 0x2d) + +#define PM8550B_ADC5_GEN3_USBC_MUX_30K_PU (PM8550B_SID << 8 | 0x33) + +/* 100k pull-up */ +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU (PM8550B_SID << 8 | 0x44) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU (PM8550B_SID << 8 | 0x45) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU (PM8550B_SID << 8 | 0x46) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU (PM8550B_SID << 8 | 0x47) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU (PM8550B_SID << 8 | 0x48) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU (PM8550B_SID << 8 | 0x49) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_100K_PU (PM8550B_SID << 8 | 0x4a) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_100K_PU (PM8550B_SID << 8 | 0x4b) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_100K_PU (PM8550B_SID << 8 | 0x4c) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550B_SID << 8 | 0x4d) + +#define PM8550B_ADC5_GEN3_USBC_MUX_100K_PU (PM8550B_SID << 8 | 0x53) + +/* 400k pull-up */ +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_400K_PU (PM8550B_SID << 8 | 0x64) +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_400K_PU (PM8550B_SID << 8 | 0x65) +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_400K_PU (PM8550B_SID << 8 | 0x66) +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_400K_PU (PM8550B_SID << 8 | 0x67) +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_400K_PU (PM8550B_SID << 8 | 0x68) +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_400K_PU (PM8550B_SID << 8 | 0x69) +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_400K_PU (PM8550B_SID << 8 | 0x6a) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_400K_PU (PM8550B_SID << 8 | 0x6b) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_400K_PU (PM8550B_SID << 8 | 0x6c) +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_400K_PU (PM8550B_SID << 8 | 0x6d) + +#define PM8550B_ADC5_GEN3_USBC_MUX_400K_PU (PM8550B_SID << 8 | 0x73) + +/* 1/3 Divider */ +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_DIV3 (PM8550B_SID << 8 | 0x8a) +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_DIV3 (PM8550B_SID << 8 | 0x8b) +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_DIV3 (PM8550B_SID << 8 | 0x8c) + +#define PM8550B_ADC5_GEN3_VPH_PWR (PM8550B_SID << 8 | 0x8e) +#define PM8550B_ADC5_GEN3_VBAT_SNS_QBG (PM8550B_SID << 8 | 0x8f) +#define PM8550B_ADC5_GEN3_VBAT_SNS_CHGR (PM8550B_SID << 8 | 0x94) +#define PM8550B_ADC5_GEN3_VBAT_2S_MID_QBG (PM8550B_SID << 8 | 0x96) +#define PM8550B_ADC5_GEN3_VBAT_2S_MID_CHGR (PM8550B_SID << 8 | 0x9d) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h new file mode 100644 index 000000000000..337e13f7f56f --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H + +/* ADC channels for PM8550VX_ADC for PMIC5 Gen3 */ +#define PM8550VS_ADC5_GEN3_OFFSET_REF(sid) ((sid) << 8 | 0x00) +#define PM8550VS_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | 0x01) +#define PM8550VS_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | 0X02) +#define PM8550VS_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | 0x03) + +#define PM8550VE_ADC5_GEN3_OFFSET_REF(sid) ((sid) << 8 | 0x00) +#define PM8550VE_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | 0x01) +#define PM8550VE_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | 0X02) +#define PM8550VE_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | 0x03) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h new file mode 100644 index 000000000000..126fc16d5b20 --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H + +#ifndef PMK8550_SID +#define PMK8550_SID 0 +#endif + +/* ADC channels for PMK8550_ADC for PMIC5 Gen3 */ +#define PMK8550_ADC5_GEN3_OFFSET_REF (PMK8550_SID << 8 | 0x00) +#define PMK8550_ADC5_GEN3_1P25VREF (PMK8550_SID << 8 | 0x01) +#define PMK8550_ADC5_GEN3_VREF_VADC (PMK8550_SID << 8 | 0x02) +#define PMK8550_ADC5_GEN3_DIE_TEMP (PMK8550_SID << 8 | 0x03) + +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM (PMK8550_SID << 8 | 0x04) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1 (PMK8550_SID << 8 | 0x05) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2 (PMK8550_SID << 8 | 0x06) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3 (PMK8550_SID << 8 | 0x07) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4 (PMK8550_SID << 8 | 0x08) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5 (PMK8550_SID << 8 | 0x09) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6 (PMK8550_SID << 8 | 0x0a) + +/* 30k pull-up */ +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_30K_PU (PMK8550_SID << 8 | 0x24) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_30K_PU (PMK8550_SID << 8 | 0x25) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_30K_PU (PMK8550_SID << 8 | 0x26) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_30K_PU (PMK8550_SID << 8 | 0x27) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_30K_PU (PMK8550_SID << 8 | 0x28) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_30K_PU (PMK8550_SID << 8 | 0x29) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_30K_PU (PMK8550_SID << 8 | 0x2a) + +/* 100k pull-up */ +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU (PMK8550_SID << 8 | 0x44) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU (PMK8550_SID << 8 | 0x45) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_100K_PU (PMK8550_SID << 8 | 0x46) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_100K_PU (PMK8550_SID << 8 | 0x47) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_100K_PU (PMK8550_SID << 8 | 0x48) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_100K_PU (PMK8550_SID << 8 | 0x49) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_100K_PU (PMK8550_SID << 8 | 0x4a) + +/* 400k pull-up */ +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_400K_PU (PMK8550_SID << 8 | 0x64) +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_400K_PU (PMK8550_SID << 8 | 0x65) +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_400K_PU (PMK8550_SID << 8 | 0x66) +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_400K_PU (PMK8550_SID << 8 | 0x67) +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_400K_PU (PMK8550_SID << 8 | 0x68) +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_400K_PU (PMK8550_SID << 8 | 0x69) +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_400K_PU (PMK8550_SID << 8 | 0x6a) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h index b1413c62ad27..ca5a0a947b3b 100644 --- a/include/dt-bindings/iio/qcom,spmi-vadc.h +++ b/include/dt-bindings/iio/qcom,spmi-vadc.h @@ -298,4 +298,82 @@ #define ADC5_GEN2_SBUx 0x94 #define ADC5_GEN2_VBAT_2S_MID 0x96 +/* ADC channels for PMIC5 Gen3 */ + +#define ADC5_GEN3_OFFSET_REF 0x00 +#define ADC5_GEN3_1P25VREF 0x01 +#define ADC5_GEN3_VREF_VADC 0x02 +#define ADC5_GEN3_DIE_TEMP 0x03 + +#define ADC5_GEN3_AMUX1_THM 0x04 +#define ADC5_GEN3_AMUX2_THM 0x05 +#define ADC5_GEN3_AMUX3_THM 0x06 +#define ADC5_GEN3_AMUX4_THM 0x07 +#define ADC5_GEN3_AMUX5_THM 0x08 +#define ADC5_GEN3_AMUX6_THM 0x09 +#define ADC5_GEN3_AMUX1_GPIO 0x0a +#define ADC5_GEN3_AMUX2_GPIO 0x0b +#define ADC5_GEN3_AMUX3_GPIO 0x0c +#define ADC5_GEN3_AMUX4_GPIO 0x0d + +#define ADC5_GEN3_CHG_TEMP 0x10 +#define ADC5_GEN3_USB_SNS_V_16 0x11 +#define ADC5_GEN3_VIN_DIV16_MUX 0x12 +#define ADC5_GEN3_VREF_BAT_THERM 0x15 +#define ADC5_GEN3_IIN_FB 0x17 +#define ADC5_GEN3_TEMP_ALARM_LITE 0x18 +#define ADC5_GEN3_IIN_SMB 0x19 +#define ADC5_GEN3_ICHG_SMB 0x1b +#define ADC5_GEN3_ICHG_FB 0xa1 + +/* 30k pull-up1 */ +#define ADC5_GEN3_AMUX1_THM_30K_PU 0x24 +#define ADC5_GEN3_AMUX2_THM_30K_PU 0x25 +#define ADC5_GEN3_AMUX3_THM_30K_PU 0x26 +#define ADC5_GEN3_AMUX4_THM_30K_PU 0x27 +#define ADC5_GEN3_AMUX5_THM_30K_PU 0x28 +#define ADC5_GEN3_AMUX6_THM_30K_PU 0x29 +#define ADC5_GEN3_AMUX1_GPIO_30K_PU 0x2a +#define ADC5_GEN3_AMUX2_GPIO_30K_PU 0x2b +#define ADC5_GEN3_AMUX3_GPIO_30K_PU 0x2c +#define ADC5_GEN3_AMUX4_GPIO_30K_PU 0x2d + +/* 100k pull-up2 */ +#define ADC5_GEN3_AMUX1_THM_100K_PU 0x44 +#define ADC5_GEN3_AMUX2_THM_100K_PU 0x45 +#define ADC5_GEN3_AMUX3_THM_100K_PU 0x46 +#define ADC5_GEN3_AMUX4_THM_100K_PU 0x47 +#define ADC5_GEN3_AMUX5_THM_100K_PU 0x48 +#define ADC5_GEN3_AMUX6_THM_100K_PU 0x49 +#define ADC5_GEN3_AMUX1_GPIO_100K_PU 0x4a +#define ADC5_GEN3_AMUX2_GPIO_100K_PU 0x4b +#define ADC5_GEN3_AMUX3_GPIO_100K_PU 0x4c +#define ADC5_GEN3_AMUX4_GPIO_100K_PU 0x4d + +/* 400k pull-up3 */ +#define ADC5_GEN3_AMUX1_THM_400K_PU 0x64 +#define ADC5_GEN3_AMUX2_THM_400K_PU 0x65 +#define ADC5_GEN3_AMUX3_THM_400K_PU 0x66 +#define ADC5_GEN3_AMUX4_THM_400K_PU 0x67 +#define ADC5_GEN3_AMUX5_THM_400K_PU 0x68 +#define ADC5_GEN3_AMUX6_THM_400K_PU 0x69 +#define ADC5_GEN3_AMUX1_GPIO_400K_PU 0x6a +#define ADC5_GEN3_AMUX2_GPIO_400K_PU 0x6b +#define ADC5_GEN3_AMUX3_GPIO_400K_PU 0x6c +#define ADC5_GEN3_AMUX4_GPIO_400K_PU 0x6d + +/* 1/3 Divider */ +#define ADC5_GEN3_AMUX1_GPIO_DIV3 0x8a +#define ADC5_GEN3_AMUX2_GPIO_DIV3 0x8b +#define ADC5_GEN3_AMUX3_GPIO_DIV3 0x8c + +#define ADC5_GEN3_VPH_PWR 0x8e +#define ADC5_GEN3_VBAT_SNS_QBG 0x8f + +#define ADC5_GEN3_VBAT_SNS_CHGR 0x94 +#define ADC5_GEN3_VBAT_2S_MID_QBG 0x96 +#define ADC5_GEN3_VBAT_2S_MID_CHGR 0x9d + +#define ADC5_GEN3_OFFSET_EXT2 0xf8 + #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */
For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs going through PBS firmware through a single register interface. This interface is implemented on an SDAM peripheral on the master PMIC PMK8550 rather than a dedicated ADC peripheral. Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com> --- .../bindings/iio/adc/qcom,spmi-vadc.yaml | 117 ++++++++++++++++-- .../iio/qcom,spmi-adc5-gen3-pm8550.h | 48 +++++++ .../iio/qcom,spmi-adc5-gen3-pm8550b.h | 97 +++++++++++++++ .../iio/qcom,spmi-adc5-gen3-pm8550vx.h | 20 +++ .../iio/qcom,spmi-adc5-gen3-pmk8550.h | 54 ++++++++ include/dt-bindings/iio/qcom,spmi-vadc.h | 78 ++++++++++++ 6 files changed, 402 insertions(+), 12 deletions(-) create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h create mode 100644 include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h