| Message ID | 20231025-topic-sm8650-upstream-mdss-v1-7-bb219b8c7a51@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/msm: Introduce display support for SM8650 | expand |
On Wed, 25 Oct 2023 at 10:35, Neil Armstrong <neil.armstrong@linaro.org> wrote: > > Add DSI PHY support for the SM8650 platform. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 27 +++++++++++++++++++++++++++ > 3 files changed, 30 insertions(+) > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > index 05621e5e7d63..7612be6c3618 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > @@ -585,6 +585,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { > .data = &dsi_phy_5nm_8450_cfgs }, > { .compatible = "qcom,sm8550-dsi-phy-4nm", > .data = &dsi_phy_4nm_8550_cfgs }, > + { .compatible = "qcom,sm8650-dsi-phy-4nm", > + .data = &dsi_phy_4nm_8650_cfgs }, > #endif > {} > }; > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > index 8b640d174785..e4275d3ad581 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > @@ -62,6 +62,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; > +extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs; > > struct msm_dsi_dphy_timing { > u32 clk_zero; > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > index 3b1ed02f644d..c66193f2dc0d 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > @@ -1121,6 +1121,10 @@ static const struct regulator_bulk_data dsi_phy_7nm_37750uA_regulators[] = { > { .supply = "vdds", .init_load_uA = 37550 }, > }; > > +static const struct regulator_bulk_data dsi_phy_7nm_98000uA_regulators[] = { > + { .supply = "vdds", .init_load_uA = 98000 }, > +}; > + > static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = { > { .supply = "vdds", .init_load_uA = 97800 }, > }; > @@ -1281,3 +1285,26 @@ const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = { > .num_dsi_phy = 2, > .quirks = DSI_PHY_7NM_QUIRK_V5_2, > }; > + > +const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs = { So, this is the same as sm8550 config, just using 400 uA less? I wonder if it makes sense to go for setting the regulator mode instead of setting the load. Nevertheless (unless you'd like to reuse sm8550 config entry): Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > + .has_phy_lane = true, > + .regulator_data = dsi_phy_7nm_98000uA_regulators, > + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators), > + .ops = { > + .enable = dsi_7nm_phy_enable, > + .disable = dsi_7nm_phy_disable, > + .pll_init = dsi_pll_7nm_init, > + .save_pll_state = dsi_7nm_pll_save_state, > + .restore_pll_state = dsi_7nm_pll_restore_state, > + .set_continuous_clock = dsi_7nm_set_continuous_clock, > + }, > + .min_pll_rate = 600000000UL, > +#ifdef CONFIG_64BIT > + .max_pll_rate = 5000000000UL, > +#else > + .max_pll_rate = ULONG_MAX, > +#endif > + .io_start = { 0xae95000, 0xae97000 }, > + .num_dsi_phy = 2, > + .quirks = DSI_PHY_7NM_QUIRK_V5_2, > +}; > > -- > 2.34.1 >
On 25/10/2023 10:03, Dmitry Baryshkov wrote: > On Wed, 25 Oct 2023 at 10:35, Neil Armstrong <neil.armstrong@linaro.org> wrote: >> >> Add DSI PHY support for the SM8650 platform. >> >> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >> --- >> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ >> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + >> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 27 +++++++++++++++++++++++++++ >> 3 files changed, 30 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >> index 05621e5e7d63..7612be6c3618 100644 >> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >> @@ -585,6 +585,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { >> .data = &dsi_phy_5nm_8450_cfgs }, >> { .compatible = "qcom,sm8550-dsi-phy-4nm", >> .data = &dsi_phy_4nm_8550_cfgs }, >> + { .compatible = "qcom,sm8650-dsi-phy-4nm", >> + .data = &dsi_phy_4nm_8650_cfgs }, >> #endif >> {} >> }; >> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >> index 8b640d174785..e4275d3ad581 100644 >> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >> @@ -62,6 +62,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; >> extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; >> extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; >> extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; >> +extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs; >> >> struct msm_dsi_dphy_timing { >> u32 clk_zero; >> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >> index 3b1ed02f644d..c66193f2dc0d 100644 >> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >> @@ -1121,6 +1121,10 @@ static const struct regulator_bulk_data dsi_phy_7nm_37750uA_regulators[] = { >> { .supply = "vdds", .init_load_uA = 37550 }, >> }; >> >> +static const struct regulator_bulk_data dsi_phy_7nm_98000uA_regulators[] = { >> + { .supply = "vdds", .init_load_uA = 98000 }, >> +}; >> + >> static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = { >> { .supply = "vdds", .init_load_uA = 97800 }, >> }; >> @@ -1281,3 +1285,26 @@ const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = { >> .num_dsi_phy = 2, >> .quirks = DSI_PHY_7NM_QUIRK_V5_2, >> }; >> + >> +const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs = { > > So, this is the same as sm8550 config, just using 400 uA less? I > wonder if it makes sense to go for setting the regulator mode instead > of setting the load. I have no idea, we keep changing this but indeed we should instead change the regulator mode, it's safer to keep it that way until we figure that out. I'll double check anyway > > Nevertheless (unless you'd like to reuse sm8550 config entry): > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Thanks, Neil > >> + .has_phy_lane = true, >> + .regulator_data = dsi_phy_7nm_98000uA_regulators, >> + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators), >> + .ops = { >> + .enable = dsi_7nm_phy_enable, >> + .disable = dsi_7nm_phy_disable, >> + .pll_init = dsi_pll_7nm_init, >> + .save_pll_state = dsi_7nm_pll_save_state, >> + .restore_pll_state = dsi_7nm_pll_restore_state, >> + .set_continuous_clock = dsi_7nm_set_continuous_clock, >> + }, >> + .min_pll_rate = 600000000UL, >> +#ifdef CONFIG_64BIT >> + .max_pll_rate = 5000000000UL, >> +#else >> + .max_pll_rate = ULONG_MAX, >> +#endif >> + .io_start = { 0xae95000, 0xae97000 }, >> + .num_dsi_phy = 2, >> + .quirks = DSI_PHY_7NM_QUIRK_V5_2, >> +}; >> >> -- >> 2.34.1 >> > >
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 05621e5e7d63..7612be6c3618 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -585,6 +585,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { .data = &dsi_phy_5nm_8450_cfgs }, { .compatible = "qcom,sm8550-dsi-phy-4nm", .data = &dsi_phy_4nm_8550_cfgs }, + { .compatible = "qcom,sm8650-dsi-phy-4nm", + .data = &dsi_phy_4nm_8650_cfgs }, #endif {} }; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 8b640d174785..e4275d3ad581 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -62,6 +62,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs; struct msm_dsi_dphy_timing { u32 clk_zero; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 3b1ed02f644d..c66193f2dc0d 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -1121,6 +1121,10 @@ static const struct regulator_bulk_data dsi_phy_7nm_37750uA_regulators[] = { { .supply = "vdds", .init_load_uA = 37550 }, }; +static const struct regulator_bulk_data dsi_phy_7nm_98000uA_regulators[] = { + { .supply = "vdds", .init_load_uA = 98000 }, +}; + static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = { { .supply = "vdds", .init_load_uA = 97800 }, }; @@ -1281,3 +1285,26 @@ const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = { .num_dsi_phy = 2, .quirks = DSI_PHY_7NM_QUIRK_V5_2, }; + +const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs = { + .has_phy_lane = true, + .regulator_data = dsi_phy_7nm_98000uA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators), + .ops = { + .enable = dsi_7nm_phy_enable, + .disable = dsi_7nm_phy_disable, + .pll_init = dsi_pll_7nm_init, + .save_pll_state = dsi_7nm_pll_save_state, + .restore_pll_state = dsi_7nm_pll_restore_state, + .set_continuous_clock = dsi_7nm_set_continuous_clock, + }, + .min_pll_rate = 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate = 5000000000UL, +#else + .max_pll_rate = ULONG_MAX, +#endif + .io_start = { 0xae95000, 0xae97000 }, + .num_dsi_phy = 2, + .quirks = DSI_PHY_7NM_QUIRK_V5_2, +};
Add DSI PHY support for the SM8650 platform. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 27 +++++++++++++++++++++++++++ 3 files changed, 30 insertions(+)