[RFC,v3,25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU.

Commit Message

Yoshinori Sato Oct. 14, 2023, 2:54 p.m. UTC

Renesas SuperH binding definition.

Signed-off-by: Yoshinori Sato <[e-mail]>
---
 .../devicetree/bindings/sh/cpus.yaml          | 45 +++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sh/cpus.yaml

Comments

Geert Uytterhoeven Oct. 18, 2023, 2:27 p.m. UTC | #1

Hi Sato-san,

On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<[e-mail]> wrote:
> Renesas SuperH binding definition.
>
> Signed-off-by: Yoshinori Sato <[e-mail]>

Thanks for your patch!

> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
> @@ -0,0 +1,45 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/sh/cpus.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas SuperH CPUs
> +
> +maintainers:
> +  - Yoshinori Sato <[e-mail]>
> +
> +description: |+
> +  The device tree allows to describe the layout of CPUs in a system through
> +  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> +  defining properties for every cpu.
> +
> +  Bindings for CPU nodes follow the Devicetree Specification, available from:
> +
> +  https://www.devicetree.org/specifications/
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:

Missing

    - jcore,j2

> +          - renesas,sh4


> +      - const: renesas,sh

I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to
"renesas,sh", though.
Is there a common base of instructions that are available on all SH cores?

Missing reg property.
Missing "device_type: true".

> +
> +  clock-frequency:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description: |
> +      CPU core clock freqency.

Perhaps a "clocks" property instead, or as an alternative?

On sh7750, you do have

    clocks = <&cpg SH7750_CPG_ICK>;

> +
> +required:
> +  - compatible
> +
> +additionalProperties: true
> +
> +examples:
> +  - |
> +        cpus {

make dt_binding_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/sh/cpus.yaml:

Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
'#address-cells' is a required property
        from schema $id: http://devicetree.org/schemas/cpus.yaml#
        Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
'#size-cells' is a required property
from schema $id: http://devicetree.org/schemas/cpus.yaml#

> +                cpu: cpu@0 {
> +                      compatible = "renesas,sh4", "renesas,sh";

Documentation/devicetree/bindings/sh/cpus.example.dts:19.28-21.19:
Warning (unit_address_vs_reg): /example-0/cpus/cpu@0: node has a unit
name, but no reg or ranges property
Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus: cpu@0:
'cache-level' is a required property
        from schema $id: http://devicetree.org/schemas/cpus.yaml#

> +                };
> +        };
> +...

Gr{oetje,eeting}s,

                        Geert

Yoshinori Sato Oct. 25, 2023, 11:14 a.m. UTC | #2

On Wed, 18 Oct 2023 23:27:43 +0900,
Geert Uytterhoeven wrote:
> 
> Hi Sato-san,
> 
> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> <[e-mail]> wrote:
> > Renesas SuperH binding definition.
> >
> > Signed-off-by: Yoshinori Sato <[e-mail]>
> 
> Thanks for your patch!
> 
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
> > @@ -0,0 +1,45 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/sh/cpus.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas SuperH CPUs
> > +
> > +maintainers:
> > +  - Yoshinori Sato <[e-mail]>
> > +
> > +description: |+
> > +  The device tree allows to describe the layout of CPUs in a system through
> > +  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> > +  defining properties for every cpu.
> > +
> > +  Bindings for CPU nodes follow the Devicetree Specification, available from:
> > +
> > +  https://www.devicetree.org/specifications/
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> 
> Missing
> 
>     - jcore,j2
> 
> > +          - renesas,sh4
> 
> 
> > +      - const: renesas,sh
> 
> I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to
> "renesas,sh", though.
> Is there a common base of instructions that are available on all SH cores?

The base instruction set is sh2.
Before that, there is sh1, but this is not compatible with Linux.
I think it would be a good idea to change this to "renesas,sh2",
but the SH7619 (SH2 CPU) would look like the following.
cpus {
	cpu: cpu@0 {
        	compatible = "renesas,sh2", "renesas,sh2";
        };
};

> Missing reg property.
> Missing "device_type: true".
> 
> > +
> > +  clock-frequency:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    description: |
> > +      CPU core clock freqency.
> 
> Perhaps a "clocks" property instead, or as an alternative?
> 
> On sh7750, you do have
> 
>     clocks = <&cpg SH7750_CPG_ICK>;
> 
> > +
> > +required:
> > +  - compatible
> > +
> > +additionalProperties: true
> > +
> > +examples:
> > +  - |
> > +        cpus {
> 
> make dt_binding_check
> DT_SCHEMA_FILES=Documentation/devicetree/bindings/sh/cpus.yaml:
> 
> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
> '#address-cells' is a required property
>         from schema $id: http://devicetree.org/schemas/cpus.yaml#
>         Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
> '#size-cells' is a required property
> from schema $id: http://devicetree.org/schemas/cpus.yaml#
> 
> > +                cpu: cpu@0 {
> > +                      compatible = "renesas,sh4", "renesas,sh";
> 
> Documentation/devicetree/bindings/sh/cpus.example.dts:19.28-21.19:
> Warning (unit_address_vs_reg): /example-0/cpus/cpu@0: node has a unit
> name, but no reg or ranges property
> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus: cpu@0:
> 'cache-level' is a required property
>         from schema $id: http://devicetree.org/schemas/cpus.yaml#
> 
> > +                };
> > +        };
> > +...
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> -- 
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [e-mail]
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

D. Jeff Dionne Oct. 25, 2023, 11:33 a.m. UTC | #3

Hi Sato-san,

We must not imply that Renesas is responsible for J2, or that it is a sanctioned SH core.

J-Core has the responsibility for maintenance of those SH ISA compatible cores.

J.

> On Oct 25, 2023, at 20:14, Yoshinori Sato <[e-mail]> wrote:
> 
> On Wed, 18 Oct 2023 23:27:43 +0900,
> Geert Uytterhoeven wrote:
>> 
>> Hi Sato-san,
>> 
>> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
>> <[e-mail]> wrote:
>>> Renesas SuperH binding definition.
>>> 
>>> Signed-off-by: Yoshinori Sato <[e-mail]>
>> 
>> Thanks for your patch!
>> 
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
>>> @@ -0,0 +1,45 @@
>>> +# SPDX-License-Identifier: GPL-2.0
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/sh/cpus.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Renesas SuperH CPUs
>>> +
>>> +maintainers:
>>> +  - Yoshinori Sato <[e-mail]>
>>> +
>>> +description: |+
>>> +  The device tree allows to describe the layout of CPUs in a system through
>>> +  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
>>> +  defining properties for every cpu.
>>> +
>>> +  Bindings for CPU nodes follow the Devicetree Specification, available from:
>>> +
>>> +  https://www.devicetree.org/specifications/
>>> +
>>> +properties:
>>> +  compatible:
>>> +    items:
>>> +      - enum:
>> 
>> Missing
>> 
>>    - jcore,j2
>> 
>>> +          - renesas,sh4
>> 
>> 
>>> +      - const: renesas,sh
>> 
>> I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to
>> "renesas,sh", though.
>> Is there a common base of instructions that are available on all SH cores?
> 
> The base instruction set is sh2.
> Before that, there is sh1, but this is not compatible with Linux.
> I think it would be a good idea to change this to "renesas,sh2",
> but the SH7619 (SH2 CPU) would look like the following.
> cpus {
> 	cpu: cpu@0 {
>        	compatible = "renesas,sh2", "renesas,sh2";
>        };
> };
> 
>> Missing reg property.
>> Missing "device_type: true".
>> 
>>> +
>>> +  clock-frequency:
>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>> +    description: |
>>> +      CPU core clock freqency.
>> 
>> Perhaps a "clocks" property instead, or as an alternative?
>> 
>> On sh7750, you do have
>> 
>>    clocks = <&cpg SH7750_CPG_ICK>;
>> 
>>> +
>>> +required:
>>> +  - compatible
>>> +
>>> +additionalProperties: true
>>> +
>>> +examples:
>>> +  - |
>>> +        cpus {
>> 
>> make dt_binding_check
>> DT_SCHEMA_FILES=Documentation/devicetree/bindings/sh/cpus.yaml:
>> 
>> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
>> '#address-cells' is a required property
>>        from schema $id: http://devicetree.org/schemas/cpus.yaml#
>>        Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
>> '#size-cells' is a required property
>> from schema $id: http://devicetree.org/schemas/cpus.yaml#
>> 
>>> +                cpu: cpu@0 {
>>> +                      compatible = "renesas,sh4", "renesas,sh";
>> 
>> Documentation/devicetree/bindings/sh/cpus.example.dts:19.28-21.19:
>> Warning (unit_address_vs_reg): /example-0/cpus/cpu@0: node has a unit
>> name, but no reg or ranges property
>> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus: cpu@0:
>> 'cache-level' is a required property
>>        from schema $id: http://devicetree.org/schemas/cpus.yaml#
>> 
>>> +                };
>>> +        };
>>> +...
>> 
>> Gr{oetje,eeting}s,
>> 
>>                        Geert
>> 
>> -- 
>> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [e-mail]
>> 
>> In personal conversations with technical people, I call myself a hacker. But
>> when I'm talking to journalists I just say "programmer" or something like that.
>>                                -- Linus Torvalds
> 
> -- 
> Yosinori Sato

Geert Uytterhoeven Oct. 25, 2023, 12:01 p.m. UTC | #4

Hi Sato-san,

On Wed, Oct 25, 2023 at 1:14 PM Yoshinori Sato
<[e-mail]> wrote:
> On Wed, 18 Oct 2023 23:27:43 +0900,
> Geert Uytterhoeven wrote:
> > On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> > <[e-mail]> wrote:
> > > Renesas SuperH binding definition.
> > >
> > > Signed-off-by: Yoshinori Sato <[e-mail]>

> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/sh/cpus.yaml

> > > +properties:
> > > +  compatible:
> > > +    items:
> > > +      - enum:
> >
> > Missing
> >
> >     - jcore,j2
> >
> > > +          - renesas,sh4
> >
> >
> > > +      - const: renesas,sh
> >
> > I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to
> > "renesas,sh", though.
> > Is there a common base of instructions that are available on all SH cores?
>
> The base instruction set is sh2.
> Before that, there is sh1, but this is not compatible with Linux.
> I think it would be a good idea to change this to "renesas,sh2",
> but the SH7619 (SH2 CPU) would look like the following.
> cpus {
>         cpu: cpu@0 {
>                 compatible = "renesas,sh2", "renesas,sh2";
>         };
> };

SH7619 would just use a single compatible value:

    compatible = "renesas,sh2".

Gr{oetje,eeting}s,

                        Geert

Geert Uytterhoeven Oct. 25, 2023, 12:04 p.m. UTC | #5

Hi Jeff,

On Wed, Oct 25, 2023 at 1:33 PM D. Jeff Dionne <[e-mail]> wrote:
> > On Oct 25, 2023, at 20:14, Yoshinori Sato <[e-mail]> wrote:
> > On Wed, 18 Oct 2023 23:27:43 +0900,
> > Geert Uytterhoeven wrote:
> >> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> >> <[e-mail]> wrote:
> >>> Renesas SuperH binding definition.
> >>>
> >>> Signed-off-by: Yoshinori Sato <[e-mail]>

> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
> >>> @@ -0,0 +1,45 @@
> >>> +# SPDX-License-Identifier: GPL-2.0
> >>> +%YAML 1.2
> >>> +---
> >>> +$id: http://devicetree.org/schemas/sh/cpus.yaml#
> >>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>> +
> >>> +title: Renesas SuperH CPUs
> >>> +
> >>> +maintainers:
> >>> +  - Yoshinori Sato <[e-mail]>
> >>> +
> >>> +description: |+
> >>> +  The device tree allows to describe the layout of CPUs in a system through
> >>> +  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> >>> +  defining properties for every cpu.
> >>> +
> >>> +  Bindings for CPU nodes follow the Devicetree Specification, available from:
> >>> +
> >>> +  https://www.devicetree.org/specifications/
> >>> +
> >>> +properties:
> >>> +  compatible:
> >>> +    items:
> >>> +      - enum:
> >>
> >> Missing
> >>
> >>    - jcore,j2

> We must not imply that Renesas is responsible for J2, or that it is a sanctioned SH core.

Compatible values do not declare any such endorsement.

> J-Core has the responsibility for maintenance of those SH ISA compatible cores.

The question is: does J2 implement the same instruction set as SH2,
i.e. can it run unmodified SH2 code?

> >>
> >>> +          - renesas,sh4
> >>
> >>
> >>> +      - const: renesas,sh
> >>
> >> I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to
> >> "renesas,sh", though.
> >> Is there a common base of instructions that are available on all SH cores?
> >
> > The base instruction set is sh2.
> > Before that, there is sh1, but this is not compatible with Linux.
> > I think it would be a good idea to change this to "renesas,sh2",

Gr{oetje,eeting}s,

                        Geert

Yoshinori Sato Oct. 25, 2023, 12:07 p.m. UTC | #6

On Wed, 25 Oct 2023 20:33:07 +0900,
D. Jeff Dionne wrote:
> 
> Hi Sato-san,
> 
> We must not imply that Renesas is responsible for J2, or that it is a sanctioned SH core.
> 
> J-Core has the responsibility for maintenance of those SH ISA compatible cores.
>

Yes. I know.
I intended to write about ISA compatibility.

> J.
> 
> > On Oct 25, 2023, at 20:14, Yoshinori Sato <[e-mail]> wrote:
> > 
> > On Wed, 18 Oct 2023 23:27:43 +0900,
> > Geert Uytterhoeven wrote:
> >> 
> >> Hi Sato-san,
> >> 
> >> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> >> <[e-mail]> wrote:
> >>> Renesas SuperH binding definition.
> >>> 
> >>> Signed-off-by: Yoshinori Sato <[e-mail]>
> >> 
> >> Thanks for your patch!
> >> 
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
> >>> @@ -0,0 +1,45 @@
> >>> +# SPDX-License-Identifier: GPL-2.0
> >>> +%YAML 1.2
> >>> +---
> >>> +$id: http://devicetree.org/schemas/sh/cpus.yaml#
> >>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>> +
> >>> +title: Renesas SuperH CPUs
> >>> +
> >>> +maintainers:
> >>> +  - Yoshinori Sato <[e-mail]>
> >>> +
> >>> +description: |+
> >>> +  The device tree allows to describe the layout of CPUs in a system through
> >>> +  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> >>> +  defining properties for every cpu.
> >>> +
> >>> +  Bindings for CPU nodes follow the Devicetree Specification, available from:
> >>> +
> >>> +  https://www.devicetree.org/specifications/
> >>> +
> >>> +properties:
> >>> +  compatible:
> >>> +    items:
> >>> +      - enum:
> >> 
> >> Missing
> >> 
> >>    - jcore,j2
> >> 
> >>> +          - renesas,sh4
> >> 
> >> 
> >>> +      - const: renesas,sh
> >> 
> >> I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to
> >> "renesas,sh", though.
> >> Is there a common base of instructions that are available on all SH cores?
> > 
> > The base instruction set is sh2.
> > Before that, there is sh1, but this is not compatible with Linux.
> > I think it would be a good idea to change this to "renesas,sh2",
> > but the SH7619 (SH2 CPU) would look like the following.
> > cpus {
> > 	cpu: cpu@0 {
> >        	compatible = "renesas,sh2", "renesas,sh2";
> >        };
> > };
> > 
> >> Missing reg property.
> >> Missing "device_type: true".
> >> 
> >>> +
> >>> +  clock-frequency:
> >>> +    $ref: /schemas/types.yaml#/definitions/uint32
> >>> +    description: |
> >>> +      CPU core clock freqency.
> >> 
> >> Perhaps a "clocks" property instead, or as an alternative?
> >> 
> >> On sh7750, you do have
> >> 
> >>    clocks = <&cpg SH7750_CPG_ICK>;
> >> 
> >>> +
> >>> +required:
> >>> +  - compatible
> >>> +
> >>> +additionalProperties: true
> >>> +
> >>> +examples:
> >>> +  - |
> >>> +        cpus {
> >> 
> >> make dt_binding_check
> >> DT_SCHEMA_FILES=Documentation/devicetree/bindings/sh/cpus.yaml:
> >> 
> >> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
> >> '#address-cells' is a required property
> >>        from schema $id: http://devicetree.org/schemas/cpus.yaml#
> >>        Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
> >> '#size-cells' is a required property
> >> from schema $id: http://devicetree.org/schemas/cpus.yaml#
> >> 
> >>> +                cpu: cpu@0 {
> >>> +                      compatible = "renesas,sh4", "renesas,sh";
> >> 
> >> Documentation/devicetree/bindings/sh/cpus.example.dts:19.28-21.19:
> >> Warning (unit_address_vs_reg): /example-0/cpus/cpu@0: node has a unit
> >> name, but no reg or ranges property
> >> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus: cpu@0:
> >> 'cache-level' is a required property
> >>        from schema $id: http://devicetree.org/schemas/cpus.yaml#
> >> 
> >>> +                };
> >>> +        };
> >>> +...
> >> 
> >> Gr{oetje,eeting}s,
> >> 
> >>                        Geert
> >> 
> >> -- 
> >> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [e-mail]
> >> 
> >> In personal conversations with technical people, I call myself a hacker. But
> >> when I'm talking to journalists I just say "programmer" or something like that.
> >>                                -- Linus Torvalds
> > 
> > -- 
> > Yosinori Sato
>

D. Jeff Dionne Oct. 25, 2023, 12:10 p.m. UTC | #7

On Oct 25, 2023, at 21:04, Geert Uytterhoeven <[e-mail]> wrote:
> 
> Hi Jeff,

Hi Geert,

> 
> On Wed, Oct 25, 2023 at 1:33 PM D. Jeff Dionne <[e-mail]> wrote:
>>> On Oct 25, 2023, at 20:14, Yoshinori Sato <[e-mail]> wrote:
>>> On Wed, 18 Oct 2023 23:27:43 +0900,
>>> Geert Uytterhoeven wrote:
>>>> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
>>>> <[e-mail]> wrote:
>>>>> Renesas SuperH binding definition.
>>>>> 
>>>>> Signed-off-by: Yoshinori Sato <[e-mail]>
> 
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
>>>>> @@ -0,0 +1,45 @@
>>>>> +# SPDX-License-Identifier: GPL-2.0
>>>>> +%YAML 1.2
>>>>> +---
>>>>> +$id: http://devicetree.org/schemas/sh/cpus.yaml#
>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>> +
>>>>> +title: Renesas SuperH CPUs
>>>>> +
>>>>> +maintainers:
>>>>> +  - Yoshinori Sato <[e-mail]>
>>>>> +
>>>>> +description: |+
>>>>> +  The device tree allows to describe the layout of CPUs in a system through
>>>>> +  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
>>>>> +  defining properties for every cpu.
>>>>> +
>>>>> +  Bindings for CPU nodes follow the Devicetree Specification, available from:
>>>>> +
>>>>> +  https://www.devicetree.org/specifications/
>>>>> +
>>>>> +properties:
>>>>> +  compatible:
>>>>> +    items:
>>>>> +      - enum:
>>>> 
>>>> Missing
>>>> 
>>>>   - jcore,j2
> 
>> We must not imply that Renesas is responsible for J2, or that it is a sanctioned SH core.
> 
> Compatible values do not declare any such endorsement.
> 
>> J-Core has the responsibility for maintenance of those SH ISA compatible cores.
> 
> The question is: does J2 implement the same instruction set as SH2,
> i.e. can it run unmodified SH2 code?

It can run all SH2 code, but an SH2 cannot run all J2 code.

The GCC compilers we use for J2 generate J2 code, not strictly SH2 code.

The main difference is SH3 dynamic shift, and (S390 derived) Compare And Swap.  The new FPU is in testing now, and AFAIK there is no FPU for SH2 but I’m not sure.

Cheers,
J.


>>>> 
>>>>> +          - renesas,sh4
>>>> 
>>>> 
>>>>> +      - const: renesas,sh
>>>> 
>>>> I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to
>>>> "renesas,sh", though.
>>>> Is there a common base of instructions that are available on all SH cores?
>>> 
>>> The base instruction set is sh2.
>>> Before that, there is sh1, but this is not compatible with Linux.
>>> I think it would be a good idea to change this to "renesas,sh2",
> 
> Gr{oetje,eeting}s,
> 
>                        Geert
> 
> -- 
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [e-mail]
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                -- Linus Torvalds

Geert Uytterhoeven Oct. 25, 2023, 12:17 p.m. UTC | #8

Hi Jeff,

On Wed, Oct 25, 2023 at 2:10 PM D. Jeff Dionne <[e-mail]> wrote:
> On Oct 25, 2023, at 21:04, Geert Uytterhoeven <[e-mail]> wrote:
> > On Wed, Oct 25, 2023 at 1:33 PM D. Jeff Dionne <[e-mail]> wrote:
> >>> On Oct 25, 2023, at 20:14, Yoshinori Sato <[e-mail]> wrote:
> >>> On Wed, 18 Oct 2023 23:27:43 +0900,
> >>> Geert Uytterhoeven wrote:
> >>>> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> >>>> <[e-mail]> wrote:
> >>>>> Renesas SuperH binding definition.
> >>>>>
> >>>>> Signed-off-by: Yoshinori Sato <[e-mail]>
> >
> >>>>> --- /dev/null
> >>>>> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml

> >>>>> +properties:
> >>>>> +  compatible:
> >>>>> +    items:
> >>>>> +      - enum:
> >>>>
> >>>> Missing
> >>>>
> >>>>   - jcore,j2
> >
> >> We must not imply that Renesas is responsible for J2, or that it is a sanctioned SH core.
> >
> > Compatible values do not declare any such endorsement.
> >
> >> J-Core has the responsibility for maintenance of those SH ISA compatible cores.
> >
> > The question is: does J2 implement the same instruction set as SH2,
> > i.e. can it run unmodified SH2 code?
>
> It can run all SH2 code, but an SH2 cannot run all J2 code.

This is exactly what

    compatible = "jcore,j2", "renesas,sh2";

represents.
Cfr. Section 2.3.1 ("compatible") of the Devicetree Specification
https://www.devicetree.org/specifications

Gr{oetje,eeting}s,

                        Geert

D. Jeff Dionne Oct. 25, 2023, 12:34 p.m. UTC | #9

> On Oct 25, 2023, at 21:17, Geert Uytterhoeven <[e-mail]> wrote:
> 
> Hi Jeff,
> 
> On Wed, Oct 25, 2023 at 2:10 PM D. Jeff Dionne <[e-mail]> wrote:
>> On Oct 25, 2023, at 21:04, Geert Uytterhoeven <[e-mail]> wrote:
>>> On Wed, Oct 25, 2023 at 1:33 PM D. Jeff Dionne <[e-mail]> wrote:
>>>>> On Oct 25, 2023, at 20:14, Yoshinori Sato <[e-mail]> wrote:
>>>>> On Wed, 18 Oct 2023 23:27:43 +0900,
>>>>> Geert Uytterhoeven wrote:
>>>>>> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
>>>>>> <[e-mail]> wrote:
>>>>>>> Renesas SuperH binding definition.
>>>>>>> 
>>>>>>> Signed-off-by: Yoshinori Sato <[e-mail]>
>>> 
>>>>>>> --- /dev/null
>>>>>>> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
> 
>>>>>>> +properties:
>>>>>>> +  compatible:
>>>>>>> +    items:
>>>>>>> +      - enum:
>>>>>> 
>>>>>> Missing
>>>>>> 
>>>>>>  - jcore,j2
>>> 
>>>> We must not imply that Renesas is responsible for J2, or that it is a sanctioned SH core.
>>> 
>>> Compatible values do not declare any such endorsement.
>>> 
>>>> J-Core has the responsibility for maintenance of those SH ISA compatible cores.
>>> 
>>> The question is: does J2 implement the same instruction set as SH2,
>>> i.e. can it run unmodified SH2 code?
>> 
>> It can run all SH2 code, but an SH2 cannot run all J2 code.
> 
> This is exactly what
> 
>    compatible = "jcore,j2", "renesas,sh2";

Oh, yes.  I agree, this is correct.  Once this is settled upon, we can change new J2 cores so they will export their ROM device tree with the sh2 fallback.

Down thread, Sato-san proposes “renesas,sh4”, “renesas,sh”  I’m not sure I understand what a “renesas,sh” base fallback is.

J.

> represents.
> Cfr. Section 2.3.1 ("compatible") of the Devicetree Specification
> https://www.devicetree.org/specifications
> 
> Gr{oetje,eeting}s,
> 
>                        Geert
> 
> -- 
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [e-mail]
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                -- Linus Torvalds

Patch

diff --git a/Documentation/devicetree/bindings/sh/cpus.yaml b/Documentation/devicetree/bindings/sh/cpus.yaml
new file mode 100644
index 000000000000..273df4dfb74e
--- /dev/null
+++ b/Documentation/devicetree/bindings/sh/cpus.yaml
@@ -0,0 +1,45 @@ 
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sh/cpus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SuperH CPUs
+
+maintainers:
+  - Yoshinori Sato <[e-mail]>
+
+description: |+
+  The device tree allows to describe the layout of CPUs in a system through
+  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
+  defining properties for every cpu.
+
+  Bindings for CPU nodes follow the Devicetree Specification, available from:
+
+  https://www.devicetree.org/specifications/
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - renesas,sh4
+      - const: renesas,sh
+
+  clock-frequency:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      CPU core clock freqency.
+
+required:
+  - compatible
+
+additionalProperties: true
+
+examples:
+  - |
+        cpus {
+                cpu: cpu@0 {
+                      compatible = "renesas,sh4", "renesas,sh";
+                };
+        };
+...