| Message ID | CAJM55Z8DXDs6LT0JrTyEMp8V6BHvsjUW7aJ8Gj+fRGsasHAi_A@mail.gmail.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | [1/4] dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/vmtest-fixes-PR | fail | merge-conflict |
Hey Emil, On Wed, Oct 25, 2023 at 11:56:41AM -0700, Emil Renner Berthing wrote: > This cache controller also supports flushing cache lines by writing > their address to a register. This can be used for cache management on > SoCs with non-coherent DMAs that predate the RISC-V Zicbom extension > such as the StarFive JH7100 SoC. I'm not really sure why we need the flag, is it not sufficient to register the cache ops on a per-compatible basis? At least for the jh7110, you're always going to want them, otherwise your system is going to be largely non-functional, right? > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > --- > Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml > b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml > index 7e8cebe21584..36ae6f48ce0b 100644 > --- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml > +++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml > @@ -81,6 +81,11 @@ properties: > The reference to the reserved-memory for the L2 Loosely > Integrated Memory region. > The reserved memory node should be defined as per the bindings > in reserved-memory.txt. > > + sifive,cache-ops: > + type: boolean > + description: | and this | is not required btw, since there's no formatting here that would need to be preserved. Cheers, Conor. > + Use this cache controller for non-standard cache management operations. > + > allOf: > - $ref: /schemas/cache-controller.yaml# > > -- > 2.40.1
Conor Dooley wrote: > Hey Emil, > > On Wed, Oct 25, 2023 at 11:56:41AM -0700, Emil Renner Berthing wrote: > > This cache controller also supports flushing cache lines by writing > > their address to a register. This can be used for cache management on > > SoCs with non-coherent DMAs that predate the RISC-V Zicbom extension > > such as the StarFive JH7100 SoC. > > I'm not really sure why we need the flag, is it not sufficient to > register the cache ops on a per-compatible basis? At least for the > jh7110 -jh7110 +jh7100 > you're always going to want them, otherwise your system is going > to be largely non-functional, right? That's right. I'll do it that way for v2. I guess my thinking was that this would be easier to just add to the device trees of other platforms that might need it. Eg. mpfs pci and jh7110 graphics. > > > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > --- > > Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml > > b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml > > index 7e8cebe21584..36ae6f48ce0b 100644 > > --- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml > > +++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml > > @@ -81,6 +81,11 @@ properties: > > The reference to the reserved-memory for the L2 Loosely > > Integrated Memory region. > > The reserved memory node should be defined as per the bindings > > in reserved-memory.txt. > > > > + sifive,cache-ops: > > + type: boolean > > + description: | > > and this | is not required btw, since there's no formatting here that > would need to be preserved. Ah, thanks. /Emil
diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml index 7e8cebe21584..36ae6f48ce0b 100644 --- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml +++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml @@ -81,6 +81,11 @@ properties: The reference to the reserved-memory for the L2 Loosely Integrated Memory region. The reserved memory node should be defined as per the bindings in reserved-memory.txt. + sifive,cache-ops: + type: boolean + description: | + Use this cache controller for non-standard cache management operations. + allOf:
This cache controller also supports flushing cache lines by writing their address to a register. This can be used for cache management on SoCs with non-coherent DMAs that predate the RISC-V Zicbom extension such as the StarFive JH7100 SoC. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> --- Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 5 +++++ 1 file changed, 5 insertions(+) - $ref: /schemas/cache-controller.yaml#