| Message ID | 20231018113622.2761997-1-chaitanya.kumar.borah@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/mtl: Support HBR3 rate with C10 phy and eDP in MTL | expand |
> -----Original Message----- > From: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com> > Sent: Wednesday, October 18, 2023 2:36 PM > To: intel-gfx@lists.freedesktop.org > Cc: Kahola, Mika <mika.kahola@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>; Sripada, Radhakrishna > <radhakrishna.sripada@intel.com>; Murthy, Arun R <arun.r.murthy@intel.com>; Borah, Chaitanya Kumar > <chaitanya.kumar.borah@intel.com>; stable@vger.kernel.org > Subject: [PATCH] drm/i915/mtl: Support HBR3 rate with C10 phy and eDP in MTL > > eDP specification supports HBR3 link rate since v1.4a. Moreover, > C10 phy can support HBR3 link rate for both DP and eDP. Therefore, do not clamp the supported rates for eDP at 6.75Gbps. > > Cc: <stable@vger.kernel.org> > > BSpec: 70073 74224 > Reviewed-by: Mika Kahola <mika.kahola@intel.com> > Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 1891c0cc187d..2c1034578984 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -430,7 +430,7 @@ static int mtl_max_source_rate(struct intel_dp *intel_dp) > enum phy phy = intel_port_to_phy(i915, dig_port->base.port); > > if (intel_is_c10phy(i915, phy)) > - return intel_dp_is_edp(intel_dp) ? 675000 : 810000; > + return 810000; > > return 2000000; > } > -- > 2.25.1
On Wed, 18 Oct 2023, Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> wrote: > eDP specification supports HBR3 link rate since v1.4a. Moreover, > C10 phy can support HBR3 link rate for both DP and eDP. Therefore, > do not clamp the supported rates for eDP at 6.75Gbps. > > Cc: <stable@vger.kernel.org> > > BSpec: 70073 74224 > > Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> For future reference, the trailers (Cc, Bspec, Signed-off-by, etc.) all go together with no blank lines in between. BR, Jani. > --- > drivers/gpu/drm/i915/display/intel_dp.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 1891c0cc187d..2c1034578984 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -430,7 +430,7 @@ static int mtl_max_source_rate(struct intel_dp *intel_dp) > enum phy phy = intel_port_to_phy(i915, dig_port->base.port); > > if (intel_is_c10phy(i915, phy)) > - return intel_dp_is_edp(intel_dp) ? 675000 : 810000; > + return 810000; > > return 2000000; > }
> -----Original Message----- > From: Jani Nikula <jani.nikula@linux.intel.com> > Sent: Monday, October 30, 2023 5:21 PM > To: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>; intel- > gfx@lists.freedesktop.org > Cc: Syrjala, Ville <ville.syrjala@intel.com>; stable@vger.kernel.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915/mtl: Support HBR3 rate with C10 > phy and eDP in MTL > > On Wed, 18 Oct 2023, Chaitanya Kumar Borah > <chaitanya.kumar.borah@intel.com> wrote: > > eDP specification supports HBR3 link rate since v1.4a. Moreover, > > C10 phy can support HBR3 link rate for both DP and eDP. Therefore, do > > not clamp the supported rates for eDP at 6.75Gbps. > > > > Cc: <stable@vger.kernel.org> > > > > BSpec: 70073 74224 > > > > Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> > > For future reference, the trailers (Cc, Bspec, Signed-off-by, etc.) all go together > with no blank lines in between. > Sure Jani, will keep in mind. Thanks Regards Chaitanya > BR, > Jani. > > > --- > > drivers/gpu/drm/i915/display/intel_dp.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > b/drivers/gpu/drm/i915/display/intel_dp.c > > index 1891c0cc187d..2c1034578984 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -430,7 +430,7 @@ static int mtl_max_source_rate(struct intel_dp > *intel_dp) > > enum phy phy = intel_port_to_phy(i915, dig_port->base.port); > > > > if (intel_is_c10phy(i915, phy)) > > - return intel_dp_is_edp(intel_dp) ? 675000 : 810000; > > + return 810000; > > > > return 2000000; > > } > > -- > Jani Nikula, Intel
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 1891c0cc187d..2c1034578984 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -430,7 +430,7 @@ static int mtl_max_source_rate(struct intel_dp *intel_dp) enum phy phy = intel_port_to_phy(i915, dig_port->base.port); if (intel_is_c10phy(i915, phy)) - return intel_dp_is_edp(intel_dp) ? 675000 : 810000; + return 810000; return 2000000; }
eDP specification supports HBR3 link rate since v1.4a. Moreover, C10 phy can support HBR3 link rate for both DP and eDP. Therefore, do not clamp the supported rates for eDP at 6.75Gbps. Cc: <stable@vger.kernel.org> BSpec: 70073 74224 Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)