| Message ID | 20231026151828.754279-2-max.chou@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Update RISC-V vector crypto to ratified v1.0.0 | expand |
On 10/26/23 12:18, Max Chou wrote: > Vector crypto spec defines the Zvkt extension that included all of the > instructions of Zvbb & Zvbc extensions and some vector instructions. > > Signed-off-by: Max Chou <max.chou@sifive.com> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/cpu_cfg.h | 1 + > target/riscv/tcg/tcg-cpu.c | 5 +++++ > 2 files changed, 6 insertions(+) > > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index e7ce977189c..d8d17dedeed 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -94,6 +94,7 @@ struct RISCVCPUConfig { > bool ext_zvknhb; > bool ext_zvksed; > bool ext_zvksh; > + bool ext_zvkt; > bool ext_zmmul; > bool ext_zvfbfmin; > bool ext_zvfbfwma; > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index c5ff03efce9..b9eaecb699c 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -499,6 +499,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > return; > } > > + if (cpu->cfg.ext_zvkt) { > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true); > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); > + } > + > /* > * In principle Zve*x would also suffice here, were they supported > * in qemu
On Fri, Oct 27, 2023 at 1:21 AM Max Chou <max.chou@sifive.com> wrote: > > Vector crypto spec defines the Zvkt extension that included all of the > instructions of Zvbb & Zvbc extensions and some vector instructions. > > Signed-off-by: Max Chou <max.chou@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu_cfg.h | 1 + > target/riscv/tcg/tcg-cpu.c | 5 +++++ > 2 files changed, 6 insertions(+) > > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index e7ce977189c..d8d17dedeed 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -94,6 +94,7 @@ struct RISCVCPUConfig { > bool ext_zvknhb; > bool ext_zvksed; > bool ext_zvksh; > + bool ext_zvkt; > bool ext_zmmul; > bool ext_zvfbfmin; > bool ext_zvfbfwma; > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index c5ff03efce9..b9eaecb699c 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -499,6 +499,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > return; > } > > + if (cpu->cfg.ext_zvkt) { > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true); > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); > + } > + > /* > * In principle Zve*x would also suffice here, were they supported > * in qemu > -- > 2.34.1 > >
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index e7ce977189c..d8d17dedeed 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -94,6 +94,7 @@ struct RISCVCPUConfig { bool ext_zvknhb; bool ext_zvksed; bool ext_zvksh; + bool ext_zvkt; bool ext_zmmul; bool ext_zvfbfmin; bool ext_zvfbfwma; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index c5ff03efce9..b9eaecb699c 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -499,6 +499,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } + if (cpu->cfg.ext_zvkt) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); + } + /* * In principle Zve*x would also suffice here, were they supported * in qemu
Vector crypto spec defines the Zvkt extension that included all of the instructions of Zvbb & Zvbc extensions and some vector instructions. Signed-off-by: Max Chou <max.chou@sifive.com> --- target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 5 +++++ 2 files changed, 6 insertions(+)