| Message ID | 20231026151828.754279-3-max.chou@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Update RISC-V vector crypto to ratified v1.0.0 | expand |
On 10/26/23 12:18, Max Chou wrote: > Signed-off-by: Max Chou <max.chou@sifive.com> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/cpu.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index a2881bfa383..5099c786415 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -131,6 +131,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), > ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed), > ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh), > + ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), > ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), > ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), > @@ -1375,6 +1376,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { > MULTI_EXT_CFG_BOOL("x-zvknhb", ext_zvknhb, false), > MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false), > MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false), > + MULTI_EXT_CFG_BOOL("x-zvkt", ext_zvkt, false), > > DEFINE_PROP_END_OF_LIST(), > };
On Fri, Oct 27, 2023 at 1:21 AM Max Chou <max.chou@sifive.com> wrote: > > Signed-off-by: Max Chou <max.chou@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index a2881bfa383..5099c786415 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -131,6 +131,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), > ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed), > ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh), > + ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), > ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), > ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), > @@ -1375,6 +1376,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { > MULTI_EXT_CFG_BOOL("x-zvknhb", ext_zvknhb, false), > MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false), > MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false), > + MULTI_EXT_CFG_BOOL("x-zvkt", ext_zvkt, false), > > DEFINE_PROP_END_OF_LIST(), > }; > -- > 2.34.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a2881bfa383..5099c786415 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -131,6 +131,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed), ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh), + ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), @@ -1375,6 +1376,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { MULTI_EXT_CFG_BOOL("x-zvknhb", ext_zvknhb, false), MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false), MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false), + MULTI_EXT_CFG_BOOL("x-zvkt", ext_zvkt, false), DEFINE_PROP_END_OF_LIST(), };
Signed-off-by: Max Chou <max.chou@sifive.com> --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+)