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[v2,14/14] disas/riscv: Replace TABs with space

Message ID 20231026151828.754279-15-max.chou@sifive.com (mailing list archive)
State New, archived
Headers show
Series Update RISC-V vector crypto to ratified v1.0.0 | expand

Commit Message

Max Chou Oct. 26, 2023, 3:18 p.m. UTC
Replaces TABs with spaces, making sure to have a consistent coding style
of 4 space indentations.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 disas/riscv.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

Alistair Francis Nov. 2, 2023, 1 a.m. UTC | #1
On Fri, Oct 27, 2023 at 1:21 AM Max Chou <max.chou@sifive.com> wrote:
>
> Replaces TABs with spaces, making sure to have a consistent coding style
> of 4 space indentations.
>
> Signed-off-by: Max Chou <max.chou@sifive.com>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  disas/riscv.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 7ea6ea050e9..e9458e574b9 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -3136,12 +3136,12 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
>                  }
>                  break;
>              case 89:
> -               switch (((inst >> 12) & 0b111)) {
> +                switch (((inst >> 12) & 0b111)) {
>                  case 0: op = rv_op_fmvp_d_x; break;
>                  }
>                  break;
>              case 91:
> -               switch (((inst >> 12) & 0b111)) {
> +                switch (((inst >> 12) & 0b111)) {
>                  case 0: op = rv_op_fmvp_q_x; break;
>                  }
>                  break;
> @@ -4579,7 +4579,7 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa)
>          break;
>      case rv_codec_zcmt_jt:
>          dec->imm = operand_tbl_index(inst);
> -       break;
> +        break;
>      case rv_codec_fli:
>          dec->rd = operand_rd(inst);
>          dec->imm = operand_rs1(inst);
> --
> 2.34.1
>
>
diff mbox series

Patch

diff --git a/disas/riscv.c b/disas/riscv.c
index 7ea6ea050e9..e9458e574b9 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -3136,12 +3136,12 @@  static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
                 }
                 break;
             case 89:
-		switch (((inst >> 12) & 0b111)) {
+                switch (((inst >> 12) & 0b111)) {
                 case 0: op = rv_op_fmvp_d_x; break;
                 }
                 break;
             case 91:
-		switch (((inst >> 12) & 0b111)) {
+                switch (((inst >> 12) & 0b111)) {
                 case 0: op = rv_op_fmvp_q_x; break;
                 }
                 break;
@@ -4579,7 +4579,7 @@  static void decode_inst_operands(rv_decode *dec, rv_isa isa)
         break;
     case rv_codec_zcmt_jt:
         dec->imm = operand_tbl_index(inst);
-	break;
+        break;
     case rv_codec_fli:
         dec->rd = operand_rd(inst);
         dec->imm = operand_rs1(inst);