Message ID | 20231110081105.3295037-1-sai.krishna.potthuri@amd.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | dt bindings: mmc: arasan,sdci: Add gate property for Xilinx platforms | expand |
On 10/11/2023 09:11, Sai Krishna Potthuri wrote: > From: Swati Agarwal <swati.agarwal@amd.com> > Please use subject prefixes matching the subsystem. You can get them for example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory your patch is touching. It's: dt-bindings > Add gate property in example node for Xilinx platforms which will be used > to ungate the DLL clock. DLL clock is required for higher frequencies like > 50MHz, 100MHz and 200MHz. > DLL clock is automatically selected by the SD controller when the SD > output clock frequency is more than 25 MHz. > > Signed-off-by: Swati Agarwal <swati.agarwal@amd.com> > Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> > Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> > --- > Note: This patch only updates the example nodes with the gate property for > Xilinx platforms. > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml index 3e99801f77d2..9075add020bf 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml @@ -226,8 +226,8 @@ examples: interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0xff160000 0x1000>; - clocks = <&clk200>, <&clk200>; - clock-names = "clk_xin", "clk_ahb"; + clocks = <&clk200>, <&clk200>, <&clk1200>; + clock-names = "clk_xin", "clk_ahb", "gate"; clock-output-names = "clk_out_sd0", "clk_in_sd0"; #clock-cells = <1>; clk-phase-sd-hs = <63>, <72>; @@ -239,8 +239,8 @@ examples: interrupt-parent = <&gic>; interrupts = <0 126 4>; reg = <0xf1040000 0x10000>; - clocks = <&clk200>, <&clk200>; - clock-names = "clk_xin", "clk_ahb"; + clocks = <&clk200>, <&clk200>, <&clk1200>; + clock-names = "clk_xin", "clk_ahb", "gate"; clock-output-names = "clk_out_sd0", "clk_in_sd0"; #clock-cells = <1>; clk-phase-sd-hs = <132>, <60>;