| Message ID | 20231114235628.534334-18-gshan@redhat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Unified CPU type check | expand |
On 11/14/23 15:56, Gavin Shan wrote: > Before it's applied: > > [gshan@gshan q]$ ./build/qemu-system-riscv64 -cpu ? > any > max > rv64 > shakti-c > sifive-e51 > sifive-u54 > thead-c906 > veyron-v1 > x-rv128 > > After it's applied: > > [gshan@gshan q]$ ./build/qemu-system-riscv64 -cpu ? > Available CPUs: > any > max > rv64 > shakti-c > sifive-e51 > sifive-u54 > thead-c906 > veyron-v1 > x-rv128 > > Signed-off-by: Gavin Shan <gshan@redhat.com> > --- > target/riscv/cpu.c | 29 ----------------------------- > target/riscv/cpu.h | 2 -- > 2 files changed, 31 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On 15/11/23 00:56, Gavin Shan wrote: > Before it's applied: > > [gshan@gshan q]$ ./build/qemu-system-riscv64 -cpu ? > any > max > rv64 > shakti-c > sifive-e51 > sifive-u54 > thead-c906 > veyron-v1 > x-rv128 > > After it's applied: > > [gshan@gshan q]$ ./build/qemu-system-riscv64 -cpu ? > Available CPUs: > any > max > rv64 > shakti-c > sifive-e51 > sifive-u54 > thead-c906 > veyron-v1 > x-rv128 > > Signed-off-by: Gavin Shan <gshan@redhat.com> > --- > target/riscv/cpu.c | 29 ----------------------------- > target/riscv/cpu.h | 2 -- > 2 files changed, 31 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 523e9a16ea..22d7422c89 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1733,35 +1733,6 @@ char *riscv_isa_string(RISCVCPU *cpu) return isa_str; } -static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) -{ - ObjectClass *class_a = (ObjectClass *)a; - ObjectClass *class_b = (ObjectClass *)b; - const char *name_a, *name_b; - - name_a = object_class_get_name(class_a); - name_b = object_class_get_name(class_b); - return strcmp(name_a, name_b); -} - -static void riscv_cpu_list_entry(gpointer data, gpointer user_data) -{ - const char *typename = object_class_get_name(OBJECT_CLASS(data)); - int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); - - qemu_printf("%.*s\n", len, typename); -} - -void riscv_cpu_list(void) -{ - GSList *list; - - list = object_class_get_list(TYPE_RISCV_CPU, false); - list = g_slist_sort(list, riscv_cpu_list_compare); - g_slist_foreach(list, riscv_cpu_list_entry, NULL); - g_slist_free(list); -} - #define DEFINE_CPU(type_name, initfn) \ { \ .name = type_name, \ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf58b0f0b5..965a44c853 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -490,9 +490,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); -void riscv_cpu_list(void); -#define cpu_list riscv_cpu_list #define cpu_mmu_index riscv_cpu_mmu_index #ifndef CONFIG_USER_ONLY
Before it's applied: [gshan@gshan q]$ ./build/qemu-system-riscv64 -cpu ? any max rv64 shakti-c sifive-e51 sifive-u54 thead-c906 veyron-v1 x-rv128 After it's applied: [gshan@gshan q]$ ./build/qemu-system-riscv64 -cpu ? Available CPUs: any max rv64 shakti-c sifive-e51 sifive-u54 thead-c906 veyron-v1 x-rv128 Signed-off-by: Gavin Shan <gshan@redhat.com> --- target/riscv/cpu.c | 29 ----------------------------- target/riscv/cpu.h | 2 -- 2 files changed, 31 deletions(-)