diff mbox series

[5/5] arm64: defconfig: Enable SC8380XP SoC base configs

Message ID 20231025142427.2661-6-quic_sibis@quicinc.com (mailing list archive)
State Changes Requested
Headers show
Series dts: qcom: Introduce SC8380XP platforms device tree | expand

Commit Message

Sibi Sankar Oct. 25, 2023, 2:24 p.m. UTC 
From: Rajendra Nayak <quic_rjendra@quicinc.com>

Enable GCC, Pinctrl and Interconnect configs for SC8380XP needed to boot
to a console shell.

Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
---
 arch/arm64/configs/defconfig | 3 +++
 1 file changed, 3 insertions(+)

Comments

Konrad Dybcio Oct. 26, 2023, 10:55 a.m. UTC | #1 
On 10/25/23 16:24, Sibi Sankar wrote:
> From: Rajendra Nayak <quic_rjendra@quicinc.com>
> 
> Enable GCC, Pinctrl and Interconnect configs for SC8380XP needed to boot
> to a console shell.
> 
> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
> ---
Please mention that =y is necessary to get console and =m would
cause issues there

Konrad
Krzysztof Kozlowski Oct. 27, 2023, 8:18 a.m. UTC | #2 
On 25/10/2023 16:24, Sibi Sankar wrote:
> From: Rajendra Nayak <quic_rjendra@quicinc.com>
> 
> Enable GCC, Pinctrl and Interconnect configs for SC8380XP needed to boot
> to a console shell.

This is generic defconfig for all platforms. You must be explicit which
SoC and board you now target. How anyone could figure out that random
set of numbers/letters like A1204XZY SoC is Qualcomm?

Best regards,
Krzysztof
Sibi Sankar Nov. 17, 2023, 4:18 a.m. UTC | #3 
Hey Konrad,


On 10/26/23 16:25, Konrad Dybcio wrote:
> 
> 
> On 10/25/23 16:24, Sibi Sankar wrote:
>> From: Rajendra Nayak <quic_rjendra@quicinc.com>
>>
>> Enable GCC, Pinctrl and Interconnect configs for SC8380XP needed to boot
>> to a console shell.
>>
>> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
>> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
>> ---
> Please mention that =y is necessary to get console and =m would
> cause issues there

Will add ^^ in the next re-spin.

-Sibi
> 
> Konrad
Sibi Sankar Nov. 17, 2023, 4:19 a.m. UTC | #4 
Hey Krzysztof,

On 10/27/23 13:48, Krzysztof Kozlowski wrote:
> On 25/10/2023 16:24, Sibi Sankar wrote:
>> From: Rajendra Nayak <quic_rjendra@quicinc.com>
>>
>> Enable GCC, Pinctrl and Interconnect configs for SC8380XP needed to boot
>> to a console shell.
> 
> This is generic defconfig for all platforms. You must be explicit which
> SoC and board you now target. How anyone could figure out that random
> set of numbers/letters like A1204XZY SoC is Qualcomm?

Thanks, will fixup the commit message.

-Sibi

> 
> Best regards,
> Krzysztof
>
diff mbox series

Patch

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 509084d35bef..78d9a21118c6 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -595,6 +595,7 @@  CONFIG_PINCTRL_SC7280=y
 CONFIG_PINCTRL_SC7280_LPASS_LPI=m
 CONFIG_PINCTRL_SC8180X=y
 CONFIG_PINCTRL_SC8280XP=y
+CONFIG_PINCTRL_SC8380XP=y
 CONFIG_PINCTRL_SDM660=y
 CONFIG_PINCTRL_SDM670=y
 CONFIG_PINCTRL_SDM845=y
@@ -1244,6 +1245,7 @@  CONFIG_SC_GCC_7180=y
 CONFIG_SC_GCC_7280=y
 CONFIG_SC_GCC_8180X=y
 CONFIG_SC_GCC_8280XP=y
+CONFIG_SC_GCC_8380XP=y
 CONFIG_SC_GPUCC_8280XP=m
 CONFIG_SC_LPASSCC_8280XP=m
 CONFIG_SDM_CAMCC_845=m
@@ -1517,6 +1519,7 @@  CONFIG_INTERCONNECT_QCOM_SC7180=y
 CONFIG_INTERCONNECT_QCOM_SC7280=y
 CONFIG_INTERCONNECT_QCOM_SC8180X=y
 CONFIG_INTERCONNECT_QCOM_SC8280XP=y
+CONFIG_INTERCONNECT_QCOM_SC8380XP=y
 CONFIG_INTERCONNECT_QCOM_SDM845=y
 CONFIG_INTERCONNECT_QCOM_SM8150=m
 CONFIG_INTERCONNECT_QCOM_SM8250=m