| Message ID | 1700577493-18538-4-git-send-email-quic_msarkar@quicinc.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | arm64: qcom: sa8775p: add cache coherency support for SA8775P | expand |
On Tue, Nov 21, 2023 at 08:08:13PM +0530, Mrinmay Sarkar wrote: > The PCIe EP controller on SA8775P supports cache coherency, hence add > the "dma-coherent" property to mark it as such. > > Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > index 7eab458..ab01efe 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -3620,6 +3620,7 @@ > <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; > interconnect-names = "pcie-mem", "cpu-pcie"; > > + dma-coherent; > iommus = <&pcie_smmu 0x0000 0x7f>; > resets = <&gcc GCC_PCIE_0_BCR>; > reset-names = "core"; What tree is this against? Both controllers are already marked as dma-coherent in mainline so this patch makes no sense (and the context also looks wrong). It was even you added them apparently: 489f14be0e0a ("arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes") Johan
On 11/21/2023 8:25 PM, Johan Hovold wrote: > On Tue, Nov 21, 2023 at 08:08:13PM +0530, Mrinmay Sarkar wrote: >> The PCIe EP controller on SA8775P supports cache coherency, hence add >> the "dma-coherent" property to mark it as such. >> >> Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> >> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> >> --- >> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> index 7eab458..ab01efe 100644 >> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> @@ -3620,6 +3620,7 @@ >> <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; >> interconnect-names = "pcie-mem", "cpu-pcie"; >> >> + dma-coherent; >> iommus = <&pcie_smmu 0x0000 0x7f>; >> resets = <&gcc GCC_PCIE_0_BCR>; >> reset-names = "core"; > What tree is this against? > > Both controllers are already marked as dma-coherent in mainline so this > patch makes no sense (and the context also looks wrong). > > It was even you added them apparently: > > 489f14be0e0a ("arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes") > > Johan Hi Johan, Yes both the RC controllers are dma-coherent and this change is for PCIe EP controller and it is inside pcie0_ep node. Actually the pcie0_ep node change is yet to apply on linux next. I just made this change on top of that and the same I mentioned in cover letter. https://lore.kernel.org/all/1699669982-7691-6-git-send-email-quic_msarkar@quicinc.com/ Thanks, Mrinmay
On Tue, Nov 21, 2023 at 09:02:41PM +0530, Mrinmay Sarkar wrote: > > On 11/21/2023 8:25 PM, Johan Hovold wrote: > > On Tue, Nov 21, 2023 at 08:08:13PM +0530, Mrinmay Sarkar wrote: > >> The PCIe EP controller on SA8775P supports cache coherency, hence add > >> the "dma-coherent" property to mark it as such. > > What tree is this against? > > > > Both controllers are already marked as dma-coherent in mainline so this > > patch makes no sense (and the context also looks wrong). > Yes both the RC controllers are dma-coherent and this change is for > PCIe EP controller and it is inside pcie0_ep node. > Actually the pcie0_ep node change is yet to apply on linux next. > I just made this change on top of that and the same I mentioned in > cover letter. Ah, thanks for clarifying, and sorry for the noise. Johan
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 7eab458..ab01efe 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3620,6 +3620,7 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; interconnect-names = "pcie-mem", "cpu-pcie"; + dma-coherent; iommus = <&pcie_smmu 0x0000 0x7f>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "core";