| Message ID | 20231120020109.3216343-1-yangcong5@huaqin.corp-partner.google.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [V3] drm/panel: boe-tv101wum-nl6: Fine tune Himax83102-j02 panel HFP and HBP | expand |
Hi, On Sun, Nov 19, 2023 at 6:01 PM Cong Yang <yangcong5@huaqin.corp-partner.google.com> wrote: > > The refresh reported by modetest is 60.46Hz, and the actual measurement > is 60.01Hz, which is outside the expected tolerance. Adjust hporch and > pixel clock to fix it. After repair, modetest and actual measurement were > all 60.01Hz. > > Modetest refresh = Pixel CLK/ htotal* vtotal, but measurement frame rate > is HS->LP cycle time(Vblanking). Measured frame rate is not only affecte > by Htotal/Vtotal/pixel clock, also affected by Lane-num/PixelBit/LineTime > /DSI CLK. Assume that the DSI controller could not make the mode that we > requested(presumably it's PLL couldn't generate the exact pixel clock?). > If you use a different DSI controller, you may need to readjust these > parameters. Now this panel looks like it's only used by me on the MTK > platform, so let's change this set of parameters. > > Fixes: 1bc2ef065f13 ("drm/panel: Support for Starry-himax83102-j02 TDDI MIPI-DSI panel") > Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> > Reviewed-by: Douglas Anderson <dianders@chromium.org> > --- > Chage since V2: > > - Update commit message. > > V2: https://lore.kernel.org/all/20231117032500.2923624-1-yangcong5@huaqin.corp-partner.google.com > > Chage since V1: > > - Update commit message. > > V1: https://lore.kernel.org/all/20231110094553.2361842-1-yangcong5@huaqin.corp-partner.google.com > --- > drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) As per previous discussions, this seems OK to me. I'll give it one more day for anyone to speak up and then plan to land it. -Doug
Hi, On Mon, Nov 20, 2023 at 10:05 AM Doug Anderson <dianders@google.com> wrote: > > Hi, > > On Sun, Nov 19, 2023 at 6:01 PM Cong Yang > <yangcong5@huaqin.corp-partner.google.com> wrote: > > > > The refresh reported by modetest is 60.46Hz, and the actual measurement > > is 60.01Hz, which is outside the expected tolerance. Adjust hporch and > > pixel clock to fix it. After repair, modetest and actual measurement were > > all 60.01Hz. > > > > Modetest refresh = Pixel CLK/ htotal* vtotal, but measurement frame rate > > is HS->LP cycle time(Vblanking). Measured frame rate is not only affecte > > by Htotal/Vtotal/pixel clock, also affected by Lane-num/PixelBit/LineTime > > /DSI CLK. Assume that the DSI controller could not make the mode that we > > requested(presumably it's PLL couldn't generate the exact pixel clock?). > > If you use a different DSI controller, you may need to readjust these > > parameters. Now this panel looks like it's only used by me on the MTK > > platform, so let's change this set of parameters. > > > > Fixes: 1bc2ef065f13 ("drm/panel: Support for Starry-himax83102-j02 TDDI MIPI-DSI panel") > > Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> > > Reviewed-by: Douglas Anderson <dianders@chromium.org> > > --- > > Chage since V2: > > > > - Update commit message. > > > > V2: https://lore.kernel.org/all/20231117032500.2923624-1-yangcong5@huaqin.corp-partner.google.com > > > > Chage since V1: > > > > - Update commit message. > > > > V1: https://lore.kernel.org/all/20231110094553.2361842-1-yangcong5@huaqin.corp-partner.google.com > > --- > > drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 8 ++++---- > > 1 file changed, 4 insertions(+), 4 deletions(-) > > As per previous discussions, this seems OK to me. I'll give it one > more day for anyone to speak up and then plan to land it. Pushed to drm-misc-fixes: cea7008190ad drm/panel: boe-tv101wum-nl6: Fine tune Himax83102-j02 panel HFP and HBP
diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c index 4f370bc6dca8..5f7e7dee8a82 100644 --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c @@ -1768,11 +1768,11 @@ static const struct panel_desc starry_qfh032011_53g_desc = { }; static const struct drm_display_mode starry_himax83102_j02_default_mode = { - .clock = 161600, + .clock = 162850, .hdisplay = 1200, - .hsync_start = 1200 + 40, - .hsync_end = 1200 + 40 + 20, - .htotal = 1200 + 40 + 20 + 40, + .hsync_start = 1200 + 50, + .hsync_end = 1200 + 50 + 20, + .htotal = 1200 + 50 + 20 + 50, .vdisplay = 1920, .vsync_start = 1920 + 116, .vsync_end = 1920 + 116 + 8,
The refresh reported by modetest is 60.46Hz, and the actual measurement is 60.01Hz, which is outside the expected tolerance. Adjust hporch and pixel clock to fix it. After repair, modetest and actual measurement were all 60.01Hz. Modetest refresh = Pixel CLK/ htotal* vtotal, but measurement frame rate is HS->LP cycle time(Vblanking). Measured frame rate is not only affecte by Htotal/Vtotal/pixel clock, also affected by Lane-num/PixelBit/LineTime /DSI CLK. Assume that the DSI controller could not make the mode that we requested(presumably it's PLL couldn't generate the exact pixel clock?). If you use a different DSI controller, you may need to readjust these parameters. Now this panel looks like it's only used by me on the MTK platform, so let's change this set of parameters. Fixes: 1bc2ef065f13 ("drm/panel: Support for Starry-himax83102-j02 TDDI MIPI-DSI panel") Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> --- Chage since V2: - Update commit message. V2: https://lore.kernel.org/all/20231117032500.2923624-1-yangcong5@huaqin.corp-partner.google.com Chage since V1: - Update commit message. V1: https://lore.kernel.org/all/20231110094553.2361842-1-yangcong5@huaqin.corp-partner.google.com --- drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)