diff mbox series

[fot-next] hisilicon/zip: Add ZIP comp high perf configuration

Message ID 20231121134024.114476-1-huangchenghai2@huawei.com (mailing list archive)
State Superseded
Delegated to: Herbert Xu
Headers show
Series [fot-next] hisilicon/zip: Add ZIP comp high perf configuration | expand

Commit Message

Chenghai Huang Nov. 21, 2023, 1:40 p.m. UTC 
To meet specific application scenarios, the function of switching between
the high performance mode and the high compression mode is added.

Use the perf_mode=0/1 configuration to set the compression high-perf mode,
0(default, high compression mode), 1(high performance mode).

Signed-off-by: Chenghai Huang <huangchenghai2@huawei.com>
---
 drivers/crypto/hisilicon/zip/zip_main.c | 64 +++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

Comments

Herbert Xu Nov. 22, 2023, 9:56 a.m. UTC | #1 
On Tue, Nov 21, 2023 at 09:40:24PM +0800, Chenghai Huang wrote:
> To meet specific application scenarios, the function of switching between
> the high performance mode and the high compression mode is added.
> 
> Use the perf_mode=0/1 configuration to set the compression high-perf mode,
> 0(default, high compression mode), 1(high performance mode).
> 
> Signed-off-by: Chenghai Huang <huangchenghai2@huawei.com>

Is it still compatible with the software algorithm implementation
when in high performance mode, in both directions?

Cheers,
Chenghai Huang Nov. 23, 2023, 11:06 a.m. UTC | #2 
On Wed, Nov 22, 2023 at 05:56PM, Herbert Xu wrote:

> On Tue, Nov 21, 2023 at 09:40:24PM +0800, Chenghai Huang wrote:
>> To meet specific application scenarios, the function of switching between
>> the high performance mode and the high compression mode is added.
>>
>> Use the perf_mode=0/1 configuration to set the compression high-perf mode,
>> 0(default, high compression mode), 1(high performance mode).
>>
>> Signed-off-by: Chenghai Huang <huangchenghai2@huawei.com>
> Is it still compatible with the software algorithm implementation
> when in high performance mode, in both directions?
>
> Cheers,

The high performance mode only improves the performance of the compression
direction, and it is compatible with the software algorithm implementation in
both directions.

The v2 patch will be sent for adding comments "These two modes only apply to
the compression direction." to the code and "crypto" prefix to the subject.

Thanks,
Chenghai
diff mbox series

Patch

diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisilicon/zip/zip_main.c
index d6672b777efc..4309cfb41374 100644
--- a/drivers/crypto/hisilicon/zip/zip_main.c
+++ b/drivers/crypto/hisilicon/zip/zip_main.c
@@ -107,6 +107,14 @@ 
 #define HZIP_CLOCK_GATED_EN		(HZIP_CORE_GATED_EN | \
 					 HZIP_CORE_GATED_OOO_EN)
 
+/* zip comp high performance */
+#define HZIP_HIGH_PERF_OFFSET		0x301208
+
+enum {
+	HZIP_HIGH_COMP_RATE,
+	HZIP_HIGH_COMP_PERF,
+};
+
 static const char hisi_zip_name[] = "hisi_zip";
 static struct dentry *hzip_debugfs_root;
 
@@ -352,6 +360,36 @@  static int hzip_diff_regs_show(struct seq_file *s, void *unused)
 	return 0;
 }
 DEFINE_SHOW_ATTRIBUTE(hzip_diff_regs);
+
+static int perf_mode_set(const char *val, const struct kernel_param *kp)
+{
+	int ret;
+	u32 n;
+
+	if (!val)
+		return -EINVAL;
+
+	ret = kstrtou32(val, 10, &n);
+	if (ret != 0 || (n != HZIP_HIGH_COMP_PERF &&
+			 n != HZIP_HIGH_COMP_RATE))
+		return -EINVAL;
+
+	return param_set_int(val, kp);
+}
+
+static const struct kernel_param_ops zip_com_perf_ops = {
+	.set = perf_mode_set,
+	.get = param_get_int,
+};
+
+/*
+ * perf_mode = 0 means enable high compression rate mode,
+ * perf_mode = 1 means enable high compression performance mode.
+ */
+static u32 perf_mode = HZIP_HIGH_COMP_RATE;
+module_param_cb(perf_mode, &zip_com_perf_ops, &perf_mode, 0444);
+MODULE_PARM_DESC(perf_mode, "ZIP high perf mode 0(default), 1(enable)");
+
 static const struct kernel_param_ops zip_uacce_mode_ops = {
 	.set = uacce_mode_set,
 	.get = param_get_int,
@@ -417,6 +455,28 @@  bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg)
 	return false;
 }
 
+static int hisi_zip_set_high_perf(struct hisi_qm *qm)
+{
+	u32 val;
+	int ret;
+
+	val = readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET);
+	if (perf_mode == HZIP_HIGH_COMP_PERF)
+		val |= HZIP_HIGH_COMP_PERF;
+	else
+		val &= ~HZIP_HIGH_COMP_PERF;
+
+	/* Set perf mode */
+	writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET);
+	ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_HIGH_PERF_OFFSET,
+					 val, val == perf_mode, HZIP_DELAY_1_US,
+					 HZIP_POLL_TIMEOUT_US);
+	if (ret)
+		pci_err(qm->pdev, "failed to set perf mode\n");
+
+	return ret;
+}
+
 static int hisi_zip_set_qm_algs(struct hisi_qm *qm)
 {
 	struct device *dev = &qm->pdev->dev;
@@ -1115,6 +1175,10 @@  static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip)
 	if (ret)
 		return ret;
 
+	ret = hisi_zip_set_high_perf(qm);
+	if (ret)
+		return ret;
+
 	hisi_zip_open_sva_prefetch(qm);
 	hisi_qm_dev_err_init(qm);
 	hisi_zip_debug_regs_clear(qm);