| Message ID | 20231126060732.31764-2-quic_luoj@quicinc.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | add qca8084 ethernet phy driver | expand |
On Sun, Nov 26, 2023 at 02:07:27PM +0800, Luo Jie wrote: > From: Vladimir Oltean <vladimir.oltean@nxp.com> > > 10G-QXGMII is a MAC-to-PHY interface defined by the USXGMII multiport > specification. It uses the same signaling as USXGMII, but it multiplexes > 4 ports over the link, resulting in a maximum speed of 2.5G per port. > > Some in-tree SoCs like the NXP LS1028A use "usxgmii" when they mean > either the single-port USXGMII or the quad-port 10G-QXGMII variant, and > they could get away just fine with that thus far. But there is a need to > distinguish between the 2 as far as SerDes drivers are concerned. Can this is split into two patches? > switch (interface) { > case PHY_INTERFACE_MODE_USXGMII: > - caps |= MAC_10000FD | MAC_5000FD | MAC_2500FD; > + caps |= MAC_10000FD | MAC_5000FD; > + fallthrough; This change seems to refer to the second paragraph, where as the rest of the code is about the first. Or does splitting this cause a bisect problem? Andrew
On 11/27/2023 1:20 AM, Andrew Lunn wrote: > On Sun, Nov 26, 2023 at 02:07:27PM +0800, Luo Jie wrote: >> From: Vladimir Oltean <vladimir.oltean@nxp.com> >> >> 10G-QXGMII is a MAC-to-PHY interface defined by the USXGMII multiport >> specification. It uses the same signaling as USXGMII, but it multiplexes >> 4 ports over the link, resulting in a maximum speed of 2.5G per port. >> >> Some in-tree SoCs like the NXP LS1028A use "usxgmii" when they mean >> either the single-port USXGMII or the quad-port 10G-QXGMII variant, and >> they could get away just fine with that thus far. But there is a need to >> distinguish between the 2 as far as SerDes drivers are concerned. > > Can this is split into two patches? This patch is a single logical for introducing the mode 10g-qxgmii, looks it's better to keep it within a single patch. > >> switch (interface) { >> case PHY_INTERFACE_MODE_USXGMII: >> - caps |= MAC_10000FD | MAC_5000FD | MAC_2500FD; >> + caps |= MAC_10000FD | MAC_5000FD; >> + fallthrough; > > This change seems to refer to the second paragraph, where as the rest > of the code is about the first. Or does splitting this cause a bisect > problem? > > Andrew Since the caps change is related to the new added interface mode 10g-qxgmii, it is reasonable to keep the changes integrated here.
On Sun, Nov 26, 2023 at 06:20:16PM +0100, Andrew Lunn wrote: > On Sun, Nov 26, 2023 at 02:07:27PM +0800, Luo Jie wrote: > > switch (interface) { > > case PHY_INTERFACE_MODE_USXGMII: > > - caps |= MAC_10000FD | MAC_5000FD | MAC_2500FD; > > + caps |= MAC_10000FD | MAC_5000FD; > > + fallthrough; > > This change seems to refer to the second paragraph, where as the rest > of the code is about the first. Or does splitting this cause a bisect > problem? I'm not sure what you're referring to here, and by over-trimming the context, this probably gives an insight into a misunderstanding. This hunk (and the next) does _not_ change what USXGMII ends up with. It moves MAC_2500FD to be under the 10G_QXGMII case from the USXGMII case, and we will _fallthrough_ from the USXGMII case into thte 10G_QXGMII case. So, USXGMII still ends up with MAC_2500FD.
diff --git a/Documentation/networking/phy.rst b/Documentation/networking/phy.rst index 1283240d7620..f64641417c54 100644 --- a/Documentation/networking/phy.rst +++ b/Documentation/networking/phy.rst @@ -327,6 +327,12 @@ Some of the interface modes are described below: This is the Penta SGMII mode, it is similar to QSGMII but it combines 5 SGMII lines into a single link compared to 4 on QSGMII. +``PHY_INTERFACE_MODE_10G_QXGMII`` + Represents the 10G-QXGMII PHY-MAC interface as defined by the Cisco USXGMII + Multiport Copper Interface document. It supports 4 ports over a 10.3125 GHz + SerDes lane, each port having speeds of 2.5G / 1G / 100M / 10M achieved + through symbol replication. The PCS expects the standard USXGMII code word. + Pause frames / flow control =========================== diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c index 966c93cbe616..1cd58723d6d0 100644 --- a/drivers/net/phy/phy-core.c +++ b/drivers/net/phy/phy-core.c @@ -141,6 +141,7 @@ int phy_interface_num_ports(phy_interface_t interface) return 1; case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_QUSGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: return 4; case PHY_INTERFACE_MODE_PSGMII: return 5; diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index c276f9482f78..803251299342 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -218,6 +218,7 @@ static int phylink_interface_max_speed(phy_interface_t interface) return SPEED_1000; case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_10G_QXGMII: return SPEED_2500; case PHY_INTERFACE_MODE_5GBASER: @@ -487,7 +488,11 @@ static unsigned long phylink_get_capabilities(phy_interface_t interface, switch (interface) { case PHY_INTERFACE_MODE_USXGMII: - caps |= MAC_10000FD | MAC_5000FD | MAC_2500FD; + caps |= MAC_10000FD | MAC_5000FD; + fallthrough; + + case PHY_INTERFACE_MODE_10G_QXGMII: + caps |= MAC_2500FD; fallthrough; case PHY_INTERFACE_MODE_RGMII_TXID: @@ -905,6 +910,7 @@ static int phylink_parse_mode(struct phylink *pl, phylink_set(pl->supported, 25000baseSR_Full); fallthrough; case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: case PHY_INTERFACE_MODE_10GKR: case PHY_INTERFACE_MODE_10GBASER: phylink_set(pl->supported, 10baseT_Half); @@ -1777,7 +1783,8 @@ static int phylink_bringup_phy(struct phylink *pl, struct phy_device *phy, if (phy->is_c45 && config.rate_matching == RATE_MATCH_NONE && interface != PHY_INTERFACE_MODE_RXAUI && interface != PHY_INTERFACE_MODE_XAUI && - interface != PHY_INTERFACE_MODE_USXGMII) + interface != PHY_INTERFACE_MODE_USXGMII && + interface != PHY_INTERFACE_MODE_10G_QXGMII) config.interface = PHY_INTERFACE_MODE_NA; else config.interface = interface; diff --git a/include/linux/phy.h b/include/linux/phy.h index e5f1f41e399c..b4ea3fa172a2 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -125,6 +125,7 @@ extern const int phy_10gbit_features_array[1]; * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN * @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII * @PHY_INTERFACE_MODE_1000BASEKX: 1000Base-KX - with Clause 73 AN + * @PHY_INTERFACE_MODE_10G_QXGMII: 10G-QXGMII - 4 ports over 10G USXGMII * @PHY_INTERFACE_MODE_MAX: Book keeping * * Describes the interface between the MAC and PHY. @@ -165,6 +166,7 @@ typedef enum { PHY_INTERFACE_MODE_10GKR, PHY_INTERFACE_MODE_QUSGMII, PHY_INTERFACE_MODE_1000BASEKX, + PHY_INTERFACE_MODE_10G_QXGMII, PHY_INTERFACE_MODE_MAX, } phy_interface_t; @@ -286,6 +288,8 @@ static inline const char *phy_modes(phy_interface_t interface) return "100base-x"; case PHY_INTERFACE_MODE_QUSGMII: return "qusgmii"; + case PHY_INTERFACE_MODE_10G_QXGMII: + return "10g-qxgmii"; default: return "unknown"; } diff --git a/include/linux/phylink.h b/include/linux/phylink.h index 875439ab45de..92bd2726cc8a 100644 --- a/include/linux/phylink.h +++ b/include/linux/phylink.h @@ -128,6 +128,7 @@ static inline unsigned int phylink_pcs_neg_mode(unsigned int mode, case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_QUSGMII: case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: /* These protocols are designed for use with a PHY which * communicates its negotiation result back to the MAC via * inband communication. Note: there exist PHYs that run @@ -680,6 +681,7 @@ static inline int phylink_get_link_timer_ns(phy_interface_t interface) case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: return 1600000; case PHY_INTERFACE_MODE_1000BASEX: